• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 392 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCLVC1310 - Input Termination

Kawai
Guru 19785 points
Other Parts Discussed in Thread: CDCLVC1310

Hi,

Please help us on the CDCLVC1310 input temination.
Our customer connects FPGA CMOS output to CDCLVC1310 input.

[Question]
Do you must  use Thevenin termination at the input of CDCLVC1310 ?

I am asking because the FPGA output do not have enough drivability (around 10mA) which may not achieve threshold level.

How should we connect such FPGA to CDCLVC1310 input ?

Best Regards,
Kawai

  • 0
    TI__Mastermind 32575 points

    Hi Kawai,

    If your FPGA's clock driver is 3.3V LVCMOS with source termination (Ro+Rs = 50 ohms) to match 50-ohm transmission line, the Thevenin termination at the PRI_INP (SEC_INP) input of CDCLVC1310.  It should follow Figure 3 in the CDCLVC1310 datasheet, except 100 ohm pull-up/pull-down resistors are not required.

    Regards,
    Alan

  • 0 in reply to Alan O
    Guru 19785 points

    Hi Alan-san,

    I appologize for my delay.

    I understood that 100ohm pull-up and 100ohm pull-down resistors are not required if sorce is teminated to the transmission line..
    * Our customer will use at 1.5V output supply. 

    Why does the test circuit show these resistors in the figure 3 ?

    This clock generator seems to have source termination.

    Best Regards,
    Kawai

  • 0 in reply to Kawai
    TI__Mastermind 32575 points

    Hi Kawai-san,

    Yes, if the driver impedance is matched to the transmission line impedance, the split termination at the load is not necessary.  I think the test circuit assumes that the driver has reasonable output current to support the load.

    However, because since the input stage is a differential buffer design, _INP should be able to switch even with attenuated single-ended input swing (0.7Vpp min = VIH_min - VIL_max) caused by weak LVCMOS drive strength or source+load terminations.

    Regards,
    Alan