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LMK03033C issue

Hi,

I use this IC in my personal project at the university. I would like to make a VFO with this IC for the shortwave band. I drive the PLL with a DDS, so I can get very little freq step without adjust big N and R.

The DDS freq range is 5MHz-5.8MHz. I can drive the PLL with differential sine wave (0.4Vp-p each), or a single ended square wave(0.5Vp-p). I can change it with solder elsewhere 2pcs 100n cap.

I made almost the basic recommended schematic.

When I start the circuit, the PLL works properly (so I think the MCU's code is good), but after a few minutes something goes wrong. Sometimes the OSCin module (or the controller section) goes wrong, and the output set on a fix freq (it can change when I change the output's div or vco div, but it's change independently from the input freq), or some output goes wrong, especially the LVPECL ones. I killed 5 ICs but I dont know where is the problem.

Please help me. I include the schematic and the pcb plan in PDFs and eagle format.

Thanks for help,

Balint

Top layer:

https://dl.dropboxusercontent.com/u/97546412/pll/1.pdf

Bottom:

https://dl.dropboxusercontent.com/u/97546412/pll/2.pdf

All:

https://dl.dropboxusercontent.com/u/97546412/pll/3.pdf

Schematic:

https://dl.dropboxusercontent.com/u/97546412/pll/4.pdf

Eagle:

https://dl.dropboxusercontent.com/u/97546412/pll/untitled.brd

https://dl.dropboxusercontent.com/u/97546412/pll/untitled.sch

  • Hello,

    Given 5 to 5.8 MHz input frequency to the PLL.  Suppose frequency multiplication by 370, which is total PLL N value.

    • 5 MHz * 370 = 1850 MHz VCO frequency
    • 5.8 MHz * 370 = 2146 MHz VCO frequency

    VCO frequency change of 296 MHz!  The VCO design allows the PLL to lock from 1843 to 2160 MHz.  However after lock, it will only be able to shift maybe +/- 15 MHz.  When a significantly new DDS input frequency is used you will need to re-program PLL2_N register to cause another lock.

    I think this is your problem, but this should not kill an IC.

    73,

    Timothy