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LMK03806 Interfacing Problem with SPI (Microwire/uWire)

Andreas Schuster2
Prodigy 20 points
Other Parts Discussed in Thread: LMK03806, CODELOADER

We use a LMK03806 Clock IC and are not able to interface the LMK with our onboard microcontroller SPI Peripheral. There was also a SoftwareSPI at hand (Manual pin toggling) which was able to configure the LMK finally.
But it is still unclear why the Hardware SPI Solution does not work, because the Timing requirements stated in the datasheet look fullfilled.
All testruns contain the same bytesequence (except 16bit zero on start for Hardware SPI without LatchEnable!)

Find more details below,

Best regards. andreas

 

HW Setup:

  • LMK03806 [2]
  • STM32 Board (ARM Cortex M4)  [1]
  • Connection directly, no buffers
  • For all Firmware tests, the Hardware setup stayed the same (including PIN's)

 

Osci Setup

Channel

Data

A

Readback

B

MOSI DATAuWire

C

SCK

D

LatchEnable LE

 

SPI Setup:

In General following Setup is used (noted otherwise)

SCK Default Low, Input valid on Rising Edge.

 

Byte Sequence:

The generated Code Sequence was generated via Ti CodeLoader 4.6.1 .

The Sequence is starting with 0x80020140. Full sequence can be found at bottom.

 

Several Firmware Options were tested:

 

Software SPI - working

SPI is implemented using manual Pin Toggling in Software.

 

[FIGURE 7 - SW SPI - Full View on init Data 0x80020140]

 

[Figure8 - SW SPI - Zoom on first Bit]

 

Here the LMK is working as expected (readback was not tested)- clock's are as required on their outputs &  Pin 33 goes to High after finishing.

 

Trigger is set here on LatchEnable.

 

Hardware SPI - not working

Here, before the 0x80020140 sequence was started, 16 empty bits are clocked out to clear all buffers.

There was also a test without the first 16 zero bits, same result.

 

[FIGURE 5 - HW SPI - Full View on init Data 0x80020140]

 

[Figure6 - HW SPI - Zoom on first Bit]

 

It can be seen here, that the bit setup is done on falling edge, and read in can be done on rising edge.

 

Trigger is set here on LatchEnable, already armed when uC program started running. So no LatchEnable happens before this point in time.

 

Hardware SPI - not working too, but strange result

Here, the SPI Settings were changed from firstEdge to secondEdge. I know that this setup should not work in general, but it was just a try because nothing else worked either.

The LMK now responds after finishing the programming sequence with enabling Pin 33 to High. But the Output Clocks are not correct. This Test was just done to

 

[FIGURE 3 - SW SPI - Full View on init Data 0x80020140]

 

 

Programming Sequence:

      0x00000f00, 

                                       0x00000F01,

                                       0x00000F02,

                                       0x00000f03,

                                       0x00000f04, 

                                       0x00000965,

                                       0x0CC80006,

                                       0x0C0C0007,

                                       0x080C0008,

                                       0x55555549,

                                       0x9C02400A,

                                       0x3400102B,

                                       0x138C006C,

                                       0x3D03826D,

                                       0x0300000E,

                                       0xC1550410,

                                       0x00000018,

                                       0x8FA8001A,

                                       0x0010001C,

                                       0x018000DD,

                                       0x040000DE,

                                       0x001F001F

 

References

[1] http://www.st.com/st-web-ui/static/active/en/resource/technical/document/user_manual/DM00039084.pdf

[2] http://www.ti.com/lit/ds/symlink/lmk03806.pdf

 

  • 0
    TI__Mastermind 28550 points

    Hello,

    Thanks for your detailed analysis of your SPI/MICROWIRE data.

    It appears on your hardware SPI send, there is a fairly large voltage spike on the LE line.  With the channels configured at 5 V/div, This spike is almost 2 V.  This would cause a premature loading of the input shift register into the decoded address register which would destroy intended programming.

    One method to do a simple confirmation of SPI write is to toggle the LD pin high/low by programming LD_MUX = 0 (logic low) and LD_TYPE = 3 (Output) and 4 (Output-inverted).

    For LMK03806, the Vil is 0.4 V, which assures a low input and the Vih is 1.6 V, which assures a high input.  You need to keep the LE below 0.4 V until LE is asserted to load the whole word.  I noticed the software SPI didn't seem to have this spike at the end.

    I suggest you place a filter capacitor on the LE/CLK/DATA line.  Perhaps 100 pF?  Then re-examine the waveform on a smaller V/div so any spike can better be seen.

    Another option to possibly help with the spike is to source terminate with a ~33 ohm resistor the output lines driving the LMK SPI inputs.

    73,

    Timothy

  • 0 in reply to Timothy T
    Prodigy 20 points

    Thanks Timothy,

    I changed the Slew rate for the SPI and the LatchEnable pins to Slow and it works right now.
    For the final design we will consider source termination and lowpass filtering

    best regards.andreas