Hi,
I'm using the 1:4 fanout buffers CDCV304 and CDCLVC1104 to distribute a 3.3V, 50% duty cycle single-ended signal over a frequency range from 5 to 180 MHz. On the input and output sides, the traces are not impedance-matched, but they are relatively short (approx. 2cm into 3.3V CMOS/TTL inputs). The buffer's supply is decoupled with 10nF, 100nF, 1uF X7R caps, which should catch current peaks sufficiently.
Now, regardless of the chip model used, I observe a degradation of the output signal between 50 and 70 MHz to the point where the receivers of the signal no longer trigger. Everything works fine for very low and very high frequencies; it is just this one notch in the mid-range response. Could this really be due to impedance mismatch, with traces this short?
Any ideas? I'll be grateful for any advice that would help me track down the source of this problem.
Thanks,
Matthias
