44.1kHz clock with low jitter recommendation

No advice yet? :/

Hi Arvind,

Thank you for your reply. That circuit has a typical jitter of 50ps. I would like better specs, around 1ps (for period jitter)  with a PLL with a truly 0 ppm frequency error since my master clock (with LVCMOS output) has only 5ppb of frequency error that I would like to preserve. Is there other available options that fulfil my requirements?

PS: in case of a jitter cleaner is there any influence of the auxiliar/internal oscillator over accuracy of the master clock reference (input) ? Is there any special specs for the VCO? Does it have to be external?

Regards,

MC

Hi VS,

The jitter specification shown in the datasheet is for PLL generated outputs. I was recommending using the deep output divider in CDCE913 to divide down a 22.5792 MHz reference to get the 44.1 kHz clock. Only the divider noise will be the contribution from our device in this scneario.

For your application this is possible only if the master clock is 22.5792 MHz. The frequency accuracy of the output will depend on the frequency accuracy of the input clock. There is no synthesis error due to our device since the output  is an integer divide of the reference clock.

Your 1ps period jitter requirement for the 44.1 KHz clock is very difficult to meet. The  jitter noise floor of most oscillocopes for long acquisition times (1000 samples of 44.1 kHz) will be limiting this measurement. We cannot use an Agilent 5052 SSA for this measurement either since it goes down only to 10 MHz.  

What type of jitter are you intereted in and how many samples? -> 1000 sample Peak-Peak Period jitter, 1000 sample Cycle Jitter or TIE?

TIE measurement will be limited due to the jitter noise floor of the oscope and Peak-Peak Period and Cycle-Cycle for the 44.1 KHz clock will not be < 1ps.

Regards

Arvind Sridhar

Hi Arvind,

I was asking for rms period jitter, but in fact these are extremely demanding requirements very dificult to obtain in practice. I may have to stick either with great accuracy with moderate jitter or very low jitter only. I can't get a master clock with ppb accuracy with a specific frequency of 22.5792MHz. As far I know it doesn't exist one with that kind of specs. I can only get ppb accuracy with a 10MHz oscillator. Still, if I use the CDCE913 to obtain 44.1kHz from a 10MHz oscillator using the internal PLL can I really get zero frequency error on the output (with the 50ps of jitter)? I'm asking this because I guess that 'zero ppm error', as stated on the datasheet ,can only be obtainable if we are dealing with an integer PLL (M/N divider) not a fractional PLL. With a ratio of 3125 and 3528 it is possible to get 11.2896MHz an then exactly 44.1kHz. Does the CDCE913 has an integer PLL?

Regards,

MC