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LMK03000 SYNC* usage?

Other Parts Discussed in Thread: LMK03200

Paragraph 6.7 in the LMK03xxx data sheet  ends with the note:

"The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the

SYNC* pin is not terminated externally the clock outputs will operate normally. If the SYNC* function is not
used, clock output synchronization is not ensured."

Does that imply that the SYNC* line has to be actively toggled between high and low at start up for  divided CLKoutx pins to be synchronized with OSCinx? That is, using the internal pull up isn't sufficient and SYNC* has to be low for some period to ensure synchronization? I don't have any bypassed clocks in my application all of them are divided or divided and delayed.

  • Hi Dennis,

    From page 16 of the LMK03000C datasheet.

    "The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided outputs are also held in a logic low state. The bypassed outputs will continue to operate normally. Shortly after the SYNC* pin goes high, the divided clock outputs are activated and will all transition to a high state simultaneously. All the outputs, divided and bypassed, will now be synchronized. Clocks in the bypassed state are not affected by SYNC* and are always synchronized with the divided output"

    The SYNC* pin has an internal pull-up resistor and needs to be forced LOW externally to disable outputs and later HIGH to enable the outputs again. Only the outputs are syncrhonized with respect to one another. The outputs are not 0 delay phase aligned with the OSCin input.

    Regards

    Arvind Sridhar

  • Arvind,

    Thanks for the note. So if I don't need the outputs to be "0 delay phase aligned" with each other and only need them to be aligned with a fixed (other than jitter) arbitrary phase relative to OSCin then I can simply leave the SYNC* with only the internal pullups? In my application I'm using the PLL to boost the frequency relative to the OSCin and only have one output. The clarification I was looking for wasn't if the phase delay relative to OSCin was zero just if it  was stable without having to toggle the SYNC*. (more an exercise in planning how many control pins I need to utilize) Probably should  order their Eval board! If the phase is too much shifted from zero, more than a few ns, it would be a problem and I'd have to tune it out.

    Regards Dennis

  • Hi Dennis,

    I think for your application, LMK03200 might be a better option. The VCO range is similar to LMK03000C and it supports 0-delay mode.

    http://www.ti.com/lit/ds/symlink/lmk03200.pdf

    Zero-delay mode is explained in detail Pages 18-23

    Regards

    Arvind Sridhar

  • Arvind

    I took a look at the 3200 and suspect you are right. We will have a certain amount of tuning in any case to line up our system clock with the higher frequency output of the PLL but doing it with it zeroed to the reference should help. The most important thing for us is that we need to result in a system where it can be calibrated and will always power up the same after that. It goes in a system that lines up several optical pulses in time with delays that all have to be "tuned" so everything optical lines up to within a few ns but once lined up needs to stay there and not move to even more accuracy at every power up. 

    So we'll start with the 3200 and see where it takes us!

    Dennis

  • Arvind

    The design I was asking about took a few turns since I asked the above questions.  Here's how we use the LMK03200, basically I have found we don't need 0-delay mode we just need to Synchronize two output channels very closely, to better than 5ps relative jitter smaller than that is better. We use the part to make bursts of pulses roughly synchronized to a system clock (of variable pulse width) as follows:

    1) Boost a 20MHz Osc input to get frequencies of pulses out that are up to 150MHz.. 

    2) We never change the input oscillator and don't need to closely Synchronize to it. We set the VCO to1200MHz. With that clock period it allows us to Synchronize closely enough to our system clock using the SYNC* as described below.

    3) Input a SYNC* input pulse, of variable width, at the system clock rate to "Gate" the output clocks on 2 channels which have different divider settings. This gives us a burst of high freq pulses on one channel with extremely low jitter (gated by the SYNC* high, we keep it low most of the time). And a pulse on the other channel divided down so it is always high at least the length of the burst. We usethe second output as a trigger pulse on a sampling scope. We've found some sampling scopes don't have trigger holdoff so you need a pulse that is the width of the burst in order to consistently trigger on the burst and see them without too much jitter pulse to pulse in the burst.

    My question is: How synchronized should I expect the 2 channels first rising edges to be?

    I'm seeing board to board variations and don't see a specification on the LMK03200 data sheet of how synchronized is SYNC*?  

    Not sure the LMK03200 is the source of the jitter variation part to part that I see but figure worth asking the question since I don't see a spec!

    Otherwise it is generating a beautiful burst of pulses with jitter lower than I can measure with my 12GHz real time scope. Just need to get my trigger pulse better synchronized. Some boards work others don't! 

    Also goes back to my first question way back when, would I be better off with the LM03000 series instead? Seems like it has less to worry about and some parts that are faster.

    thanks

    Dennis