Paragraph 6.7 in the LMK03xxx data sheet ends with the note:
"The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the
SYNC* pin is not terminated externally the clock outputs will operate normally. If the SYNC* function is not
used, clock output synchronization is not ensured."
Does that imply that the SYNC* line has to be actively toggled between high and low at start up for divided CLKoutx pins to be synchronized with OSCinx? That is, using the internal pull up isn't sufficient and SYNC* has to be low for some period to ensure synchronization? I don't have any bypassed clocks in my application all of them are divided or divided and delayed.