Questions Regarding Clock Buffer Chip: CDCLVC1104

Hi Alan,

Thank for your reply.

Kindly find attached the input and output plots as observed in a DSO scope.

Fig. 1: Input to the buffer circuit on pin1. Chip is enabled by applying 3.3V to the enable pin (pin2).

Fig 2: Output of the buffer circuit on channel 1 with channels 2,3 and 4 open.

Thank you.

Valay Shah

Hi Alan,

In case of the sine wave of 300 MHz the output is an undistorted replica of the input. Kindly see the attached input and output waveforms for this case (fig. 1).

But again when I feed the sine wave of 40 MHz, some distortion is seen in the output (fig. 2).

Fig. 1: Buffer circuit channel 1 output when the input signal is 300 MHz (input on pin1).

Fig. 2: Buffer circuit channel 1 output when the input signal is 40 MHz (input on pin1).

Kindly let me know if I am missing on something.

Thank you.

Valay Shah

Can you pls send scope screenshots of the clock signal at the device input pin?

Regards,

Alan

What are the high and low DC levels of the pulse signal at the device input pin?  The swing appears too small at less than 500 mVpp.  Make sure you meet the input level specs per my earlier reply.

Regards,

Alan

Hi Alan,

Below are the screenshots of the clock input signal on pin1 as well as on the SMA connector. Here I have amplified the input clock signal. They do look distorted.

Fig 6: Screenshot of the board with 1:4 buffer chip and probe setup. Position 1 and 2 (numbers in red) are the two positions I will be probing to check the input clock signal.

Fig. 7: Screenshot of the clock buffer input signal at position 1 of fig. 6 (i.e.: at the SMA connector).

Fig. 8: Screenshot of the clock input signal at pin 1 of the 1:4 buffer chip (i.e.: at Position 2 of fig. 6).

Thank you.

Valay Shah

Valay,

Yes, these input waveforms will be problematic.  I'm not sure what you're using to drive the device and what are the transmission line characteristics, so hopefully you can figure out how to improve the input signal integrity.

Regards,
Alan

Hi Alan,

As you suggested I did amplified the input clock signal in order to comply with the min input signal specs (which I still have the doubt). Does this levels has to comply with the datasheet numbers as shown below?

Fig. 9: Screenshot of datasheet with input signal specifications.

1)  Does the above table mean that lower level of my clock input has to be VIL=1.05 V and the upper level VIH=2.25V ?

2) Or do I need to only worry about the voltage swing ? In the new measurements I am using Voltage swing of ~ 800 mV as shown in fig 7 and 8 (in previous thread) but still there is a distortion in the output signal.

3) My input clock signal is two sided (i.e.: positive and negative). Do this chip accept only one sided signal (only positive) ?

4) What is the suggested input impedance on the pin 1 ? 

Thank you.

Valay Shah