I'm interested in using an LMK00304 to distribute a 100 MHz sinewave clock to three separate PLLs. The 100 MHz clock originates from a GPS-disciplined OCXO, with very good phase noise properties (-160 dBc/Hz floor, -140 dBc/Hz at 1k offset).
In one of the videos produced by TI regarding phase noise and jitter measurement on clock buffers, there's a mention of using an amplifier and limiter (the video shows a number of connectorized parts) to improve the rise time of a 100 MHz OCXO. Would anyone be able to share how this is done, and what kind of slew rates can be achieved with this setup? A quick back-of-the-envelope calculation using a Mini-circuits RLM-33+ limiter (+10 dBm out, +20 dBm in) indicates that I should get about 2 V/ns, which is still shy of the 3 V/ns that the LMK00304 needs for optimum performance. What other options do I have to improve the slew rate?
What about a device like the ONET1191P? Would its jitter be worse than that of the LMK00304? I see that the jitter spec is about 0.4 ps, which is quite high compared to the additive jitter of the clock buffer.
Thanks in advance.