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Hi Eltaher,
I have forwarded your request to the team that supports this product.
Regard
Arvind Sridhar
Hi Amr,
In a traditional PLL application, the phase error reaches a steady state - can you elaborate more on the specification you require?
Gabe
Hi Amr,
By detect, do you mean you wish to set some sort of limit where if the two phases are out of alignment by N degrees then a digital signal is triggered or do you wish to be able to correlate the degrees of mismatch to a voltage?
Gabe
Hi Amr,
Unfortunately we do not characterize our devices in open loop configurations so these specifications are not readily available.
Gabe
Hi,
Closed loop configuration for this device is similar to what is shown below.
This would not satisfy your needs for the device.
Gabe