VCXO recommendation for LMK04816

Hi Niels,

In general, the application of LMK device assume a fixed frequency input clock. LMK04816 can support up to three discrete, fixed freq input clocks. Bear in mind that the first PLL PDF has to be the same for all three inputs or otherwise the loop response will be different. 

With a variable input clock freq, you could still keep PDF constant by keep changing the R-counter value. However, in your case, you have a very big freq variation, from 1KHz to 100MHz. That means the highest PDF is 1KHz, which is quite low and this limited your choice of the VCXO freq. I estimated the highest VCXO freq is 15MHz. As such, the highest 2nd PLL PDF is 30MHz (with doubler enabled). This freq is not very high, so the phase noise of the 2nd PLL is not optimized.

in summary, you could have variable clock freq input, but you have to change the 1st PLL R-counter simultaneously. The overall phase noise is not optimized as all the PDF freq are not high enough.

Hi Noel,

it's possible for me to change the LMK04816 register settings according to the input frequency, since I know the input frequency at power-up.

But the product will be used in very different applications with different input frequencies.

How do I have to design the loop-filters and VCXO in this case?

I need a loop-filter and VCXO configuration that allows the LMK04816 to work with input fequencies from 1kHz - 100MHz. LMK04816 register settings can be different for each input frequency.

I am looking forward to your answer.

King Regards,
Niels

Hi Niels,

The Clock Design Tool (http://www.ti.com/tool/clockdesigntool) will assist you to configure the loop filters as well as divider values. However, as Noel mentioned such a vast frequency input range would require a common PLL1 phase detector frequency across all input frequencies in order for the loop filter to be optimal. (ie, a loop filter is designed for a specific PLL phase detector frequency and changing that frequency will cause the loop response to be non-optimal).

In your case, as Noel mentioned, plan on having a PLL1 PDF of 1 kHz and use the R divider appropriately depending on the input frequency. His other concerns will continue to hold however.

Gabe

Hi Gabe and Noel,

I played a lot with the Clock Design Tool, and it seems as if the LMK04816 is not able to deal with different input frequencies without changing the VCXO frequency and loop filter.

If I change the input frequency or some register settings, the tool often automatically changes the VCXO frequency.

But changing VCXO frequency or loop filter means populating different components on the pcb. This is not an option.

I need a solution that allows me programming the device in a way that input frequencies from slow (e.g.1kHz) up to 100MHz result in output frequencies in the range of 10MHz to 100MHz.
Without changing component on the board.

Is this possible?

If not, is it possible if the lower frequency limit is at 10kHz, 100kHz, ...?

What is the best VCXO frequency?
Which VCXO tuning range is required?
Loop filter dimension?

Regards,

Niels

One additional comment:

I want to use it in Zero-Delay-Mode with external loopback.

Does this change anything?

Regards,
Niels