Hello,
We have a new design that is using the LMK04828B. Our current registers are shown below. Currently we have both PLL1 and PLL2 locked. VCO1 = 3G, CLKIN0 = 20M, external VCO = 100M,
We would like DCLKout 0 = 100M (which works fine if SDCLKout is PD)
We would like SDCLKout 1 = 8M ( continuous mode for now, but pulser for system)
Problem:
When we turn on SDCLKout 1, the DCLKout 0 signal is contaminated. If we PD DCLKout0 and
turn the SDCLKout 1 mux to DCLKout 0 the signal quality out on SDCLKout 1 is still bad.
Both DCLKout0 and SDCLKout1 are LVPECL to the ADC. Termination topology is the same as
the TI reference design.
Regards,
John
static const DEVICE_DATA defaultData [NUM_REGISTERS] =
{
{ 0x0000, 0x90}, // Init
{ 0x0000, 0x10},
{ 0x0002, 0x00},
{ 0x0003, 0x00},
{ 0x0004, 0x00},
{ 0x0005, 0x00},
{ 0x0006, 0x00},
{ 0x000c, 0x00},
{ 0x000d, 0x00},
{ 0x0100, 0x1e},
{ 0x0101, 0x55},
{ 0x0103, 0x00},
//{ 0x0104, 0x03},
{ 0x0104, 0x20},
//{ 0x0104, 0x23},
{ 0x0105, 0x00},
{ 0x0106, 0x71},
{ 0x0107, 0x05},
{ 0x0108, 0x1e},
{ 0x0109, 0x55},
{ 0x010b, 0x00},
{ 0x010c, 0x03},
{ 0x010d, 0x00},
{ 0x010e, 0xf0},
{ 0x010f, 0x11},
{ 0x0110, 0x1e},
{ 0x0111, 0x55},
{ 0x0113, 0x00},
{ 0x0114, 0x03},
{ 0x0115, 0x00},
{ 0x0116, 0xf0},
{ 0x0117, 0x11},
{ 0x0118, 0x18},
{ 0x0119, 0x55},
{ 0x011b, 0x00},
{ 0x011c, 0x02},
{ 0x011d, 0x00},
{ 0x011e, 0xf9},
{ 0x011f, 0x33},
{ 0x0120, 0x08},
{ 0x0121, 0x55},
{ 0x0123, 0x00},
{ 0x0124, 0x02},
{ 0x0125, 0x00},
{ 0x0126, 0xf9},
{ 0x0127, 0x00},
{ 0x0128, 0x08},
{ 0x0129, 0x55},
{ 0x012b, 0x00},
{ 0x012c, 0x02},
{ 0x012d, 0x00},
{ 0x012e, 0xf9},
{ 0x012f, 0x00},
{ 0x0130, 0x06},
{ 0x0131, 0x55},
{ 0x0133, 0x00},
{ 0x0134, 0x02},
{ 0x0135, 0x00},
{ 0x0136, 0xf9},
{ 0x0137, 0x33},
{ 0x0138, 0x20},
{ 0x0139, 0x02},
//{ 0x0139, 0x03},
{ 0x013a, 0x01},
{ 0x013b, 0x77},
{ 0x013c, 0x00},
{ 0x013d, 0x08},
{ 0x013e, 0x03},
{ 0x013f, 0x00},
//{ 0x0140, 0x0a},
{ 0x0140, 0x01},
{ 0x0141, 0x00},
{ 0x0142, 0x00},
{ 0x0143, 0x11},
{ 0x0144, 0x00},
{ 0x0145, 0x7f},
//{ 0x0146, 0x1f},
{ 0x0146, 0x0f},
//{ 0x0147, 0x1a},
{ 0x0147, 0x3a},
{ 0x0148, 0x02},
{ 0x0149, 0x42},
{ 0x014a, 0x03},
{ 0x014b, 0x16},
{ 0x014c, 0x00},
{ 0x014d, 0x00},
{ 0x014e, 0xc0},
{ 0x014f, 0x7f},
{ 0x0150, 0x03},
{ 0x0151, 0x02},
{ 0x0152, 0x00},
{ 0x0153, 0x00},
{ 0x0154, 0x01},
{ 0x0155, 0x00},
{ 0x0156, 0x14},
{ 0x0157, 0x00},
{ 0x0158, 0x00},
{ 0x0159, 0x00},
{ 0x015a, 0x05},
{ 0x015b, 0x1f},
{ 0x015c, 0x20},
{ 0x015d, 0x00},
{ 0x015e, 0x00},
{ 0x015f, 0x0b},
{ 0x0160, 0x00},
{ 0x0161, 0x01},
{ 0x0162, 0x44},
{ 0x0163, 0x00},
{ 0x0164, 0x00},
{ 0x0165, 0x0c},
{ 0x017c, 0x21}, // Program before PLL2 register
{ 0x017d, 0x51}, // to optimize VCO1 noise performance
{ 0x0166, 0x00}, // PLL2 registers
{ 0x0167, 0x00}, //
{ 0x0168, 0x0f}, //
{ 0x0169, 0x5d},
{ 0x016a, 0x40},
{ 0x016b, 0x01},
{ 0x016c, 0x00},
{ 0x016d, 0x00},
{ 0x016e, 0x13},
{ 0x0173, 0x00},
//{ 0x0182, 0x0}, ?
//{ 0x0183, 0x0}, ?
//{ 0x0184, 0x0}, ?
//{ 0x0185, 0x0}, ?
//{ 0x0188, 0x0}, ?
{ 0x1ffd, 0x00},
{ 0x1ffe, 0x00},
{ 0x1fff, 0x53},
};
From: John Tauch [mailto:jtauch@dallaslogic.com]
Sent: Monday, April 14, 2014 12:00 PM
To: An Duy Bui
Subject: RE: LMK and ADC Registers
Sent: Monday, April 14, 2014 12:00 PM
To: An Duy Bui
Subject: RE: LMK and ADC Registers
From: anduybui@gmail.com
To: jtauch@dallaslogic.com
Subject: RE: LMK and ADC Registers
Date: Mon, 14 Apr 2014 11:22:59 -0500
To: jtauch@dallaslogic.com
Subject: RE: LMK and ADC Registers
Date: Mon, 14 Apr 2014 11:22:59 -0500
static const DEVICE_DATA defaultData [NUM_REGISTERS] =
{
{ 0x0000, 0x90}, // Init
{ 0x0000, 0x10},
{ 0x0002, 0x00},
{ 0x0003, 0x00},
{ 0x0004, 0x00},
{ 0x0005, 0x00},
{ 0x0006, 0x00},
{ 0x000c, 0x00},
{ 0x000d, 0x00},
{ 0x0100, 0x1e},
{ 0x0101, 0x55},
{ 0x0103, 0x00},
//{ 0x0104, 0x03},
{ 0x0104, 0x23},
{ 0x0105, 0x00},
{ 0x0106, 0xf0},
{ 0x0107, 0x55},
{ 0x0108, 0x1e},
{ 0x0109, 0x55},
{ 0x010b, 0x00},
{ 0x010c, 0x03},
{ 0x010d, 0x00},
{ 0x010e, 0xf0},
{ 0x010f, 0x11},
{ 0x0110, 0x1e},
{ 0x0111, 0x55},
{ 0x0113, 0x00},
{ 0x0114, 0x03},
{ 0x0115, 0x00},
{ 0x0116, 0xf0},
{ 0x0117, 0x11},
{ 0x0118, 0x18},
{ 0x0119, 0x55},
{ 0x011b, 0x00},
{ 0x011c, 0x02},
{ 0x011d, 0x00},
{ 0x011e, 0xf9},
{ 0x011f, 0x33},
{ 0x0120, 0x08},
{ 0x0121, 0x55},
{ 0x0123, 0x00},
{ 0x0124, 0x02},
{ 0x0125, 0x00},
{ 0x0126, 0xf9},
{ 0x0127, 0x00},
{ 0x0128, 0x08},
{ 0x0129, 0x55},
{ 0x012b, 0x00},
{ 0x012c, 0x02},
{ 0x012d, 0x00},
{ 0x012e, 0xf9},
{ 0x012f, 0x00},
{ 0x0130, 0x06},
{ 0x0131, 0x55},
{ 0x0133, 0x00},
{ 0x0134, 0x02},
{ 0x0135, 0x00},
{ 0x0136, 0xf9},
{ 0x0137, 0x33},
{ 0x0138, 0x20},
//{ 0x0139, 0x02},
{ 0x0139, 0x03},
{ 0x013a, 0x01},
{ 0x013b, 0x77},
{ 0x013c, 0x00},
{ 0x013d, 0x08},
{ 0x013e, 0x03},
{ 0x013f, 0x00},
//{ 0x0140, 0x0a},
{ 0x0140, 0x02},
{ 0x0141, 0x00},
{ 0x0142, 0x00},
{ 0x0143, 0x11},
{ 0x0144, 0x00},
{ 0x0145, 0x7f},
//{ 0x0146, 0x1f},
{ 0x0146, 0x0f},
{ 0x0147, 0x1a},
{ 0x0148, 0x02},
{ 0x0149, 0x42},
{ 0x014a, 0x03},
{ 0x014b, 0x16},
{ 0x014c, 0x00},
{ 0x014d, 0x00},
{ 0x014e, 0xc0},
{ 0x014f, 0x7f},
{ 0x0150, 0x03},
{ 0x0151, 0x02},
{ 0x0152, 0x00},
{ 0x0153, 0x00},
{ 0x0154, 0x78},
{ 0x0155, 0x00},
{ 0x0156, 0x14},
{ 0x0157, 0x00},
{ 0x0158, 0x00},
{ 0x0159, 0x00},
{ 0x015a, 0x64},
{ 0x015b, 0xdf},
{ 0x015c, 0x20},
{ 0x015d, 0x00},
{ 0x015e, 0x00},
{ 0x015f, 0x0b},
{ 0x0160, 0x00},
{ 0x0161, 0x08},
{ 0x0162, 0x44},
{ 0x0163, 0x00},
{ 0x0164, 0x00},
{ 0x0165, 0x0c},
{ 0x017c, 0x15}, // Program before PLL2 register
{ 0x017d, 0x33}, // to optimize VCO1 noise performance
{ 0x0166, 0x00},// PLL2 registers
{ 0x0167, 0x00}, //
{ 0x0168, 0x78}, //
{ 0x0169, 0x5d},
{ 0x016a, 0x60},
{ 0x016b, 0x00},
{ 0x016c, 0x00},
{ 0x016d, 0x00},
{ 0x016e, 0x13},
{ 0x0173, 0x00},
// { 0x017c, 0x0},
// { 0x017d, 0x0},
//{ 0x0182, 0x0}, ?
//{ 0x0183, 0x0}, ?
//{ 0x0184, 0x0}, ?
//{ 0x0185, 0x0}, ?
//{ 0x0188, 0x0}, ?
{ 0x1ffd, 0x00},
{ 0x1ffe, 0x00},
{ 0x1fff, 0x53},
};
