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Phase noise measurement in LMK04826B

Nithin P
Prodigy 140 points
Other Parts Discussed in Thread: LMK04826BEVM

Hello All,

I used Clock Design tool and based on the attached screenshot values generated 500 MHz clock from LMK04826BEVM. I can see 500MHz with a duty cycle of 51.9% in a DCA. 

When I connect the output of DCLKOut0 to SSA, I can see that the phase noise measurement is around 150ps which is not good since in the documentation I can see we can achieve phase noise around 100fs. Please can anyone suggest if there are any ways to improve my phase noise?

Best Regards,

NP.

  • 0
    TI__Mastermind 28550 points

    Hello,

    It seems your issue is that PLL2 phase detector frequency is so small.  You should try for a 100 MHz, 125 MHz, etc.

    Choosing Loop Bandwidth for PLLs
    http://e2e.ti.com/support/clocks/m/videos__files/664163.aspx

       See slide 17 illustrating impact of narrower phase detector frequency

       See slide 34 discussing the poor input to output frequency relationship/benefit with dual loop.

    73,

    Timothy

  • 0 in reply to Timothy T
    Prodigy 140 points

    Hello Timothy,

    Many thanks for your answer and the reference pdf which you have given. It is very helpful. But as mentioned by you in slide number 17, you can see that with 100kHz PDF we should be able to get 457.3fs. I have 160kHz, so even with that frequency I should be able to generate a phase noise which is in the range of hundreds of fs. 

    I am able to generate a 460fs phase noise with slightly different parameters.

    PLL2ref = 122.88MHz

    PLL2_R = 9

    PLL2_N = 61

    PLL2_N_PRE = 3

    PLL2 PDF = 8.777 MHz

    The values with which I wanted to generate 2500MHz signal at PLL2 output (so that I can generate 500MHz by dviding by 5) was suggested by Clock Design tool and there if I see phase noise value , I can see it should generate 720fs but it is not generated.

    Best Regards,

    NP.