Hello.
I have a complex clock distribution issue with rather unusual requirements. This is part of a timing instrument.
I have 2 LVDS clocks input (A and B). Clock frequency is 10 MHz.
I want to distribute them to:
- 1 LVCMOS output for clock A, always on.
- 1 LVCMOS output for clock B, always on.
- 2 of any differential outputs, clock A or B, can be disabled.
- 1 LVCMOS outputs, clock A or B, can be disabled.
The differential outputs could be combinations of A and B: both A, both B, or A and B (B and A is optional). This is the issue with almost all clock buffers, because they only include mux and not cross-point switches.
There is other requirements:
- The jitter on the differential outputs is critical, it must stay under 5ps.
- The propagation delay must depend linearly of the temperature, or stay within 200ps for -40 to 80 deg C.
- Only 3.3V is available, power consumption should be minimized, 100mA max when differential outputs are off. There is another 3.3V supply that is disabled when the differential outputs are not needed.
- Cost is not an issue.
My current solution is to use two LMK00304, one for each clock, and put a 2:2 cross-point switch after, that is powered down when not needed. Two LVDS to LVCMOS translators, that are also powered down when not needed, give me the last LVCMOS outputs.
This is 5 components total. It look overcomplicated, and I am wondering if I missed something, like a single chip that will do the job.
Thanks!
