Other Parts Discussed in Thread: CDCE913
Hi,
We are using CDCE913 as clock source for Xilinx FPGA, please see below our schematic, code and the issue what we have while we configure for our expected frequency,
//Call the low level Xilinx IIC controller drivers to complete the I2C write transaction.
sent_byte_count = XIic_DynSend(I2C_Base_Address, dev_address_widener, I2C_write_buffer, 2, XIIC_STOP);
When programmed with default register values using byte write operation, programming succeeds and generates expected frequency values ( Y1, Y2, Y3 generates same output freq as Input freq X1 ). Byte writes as follows ( write operation in the same order as below ) :
0x85 CDCE913_XCSEL 0x50
0x82 CDCE913_GCR_Y1_A 0xB4
0x83 CDCE913_GCR_Y1_B 0x01
0x84 CDCE913_GCR_Y1_C 0x02
0x96 CDCE913_PDIV2 0x01
0x97 CDCE913_PDIV3 0x01
0x99 CDCE913_PLL1_0_B 0x40
0x9A CDCE913_PLL1_0_C 0x04
0x9B CDCE913_PLL1_0_D 0x08
0x90 CDCE913_SSC1_A 0x00
0x91 CDCE913_SSC1_B
0x00
0x92 CDCE913_SSC1_C 0x00
0x94 CDCE913_MUX_Y2Y3STATE 0xED
0x95 CDCE913_Y2Y3_OUTPUT_STATE 0x02
0x86 CDCE913_BCOUNT 0x20
For different frequency generation, byte write operation fails while writing to 0x96 & 0x94 registers ( 0x16h , 0x14h registers as in CDCE913 datasheet ).
0x85 CDCE913_XCSEL 0x40
0x82 CDCE913_GCR_Y1_A 0xBC
0x83 CDCE913_GCR_Y1_B 0x05
0x84 CDCE913_GCR_Y1_C 0xFF
0x96 CDCE913_PDIV2 0x83
0x97 CDCE913_PDIV3 0x02
0x99 CDCE913_PLL1_0_B 0x80
0x9A CDCE913_PLL1_0_C 0x8B
0x9B CDCE913_PLL1_0_D 0xAB
0x90 CDCE913_SSC1_A 0xFF
0x91 CDCE913_SSC1_B
0xFF
0x92 CDCE913_SSC1_C 0xFF
0x94 CDCE913_MUX_Y2Y3STATE 0x6F
0x95 CDCE913_Y2Y3_OUTPUT_STATE 0xFF
0x86 CDCE913_BCOUNT 0x01
