• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 21 subscribers
  • Views 362 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCE62002 - Using for SDI application

Kawai
Guru 19785 points
Other Parts Discussed in Thread: CDCE62002

Hi Team,

Our customer is evaluating CDCE62002 for SDI application. However they have problem that they cannot pass the timing jitter and alignment jitter specification.

Could you tell us the best loop filter design which can commonly used in the following condition ?

Case1) LVCMOS 148.5MHz --> LVCMOS 148.5MHz
Case2) LVCMOS 74.25MHz --> LVCMOS 74.25MHz
Case3) LVCMOS 27MHz --> LVCMOS 27MHz
Case4) LVCMOS 13.5MHz --> LVCMOS 13.5MHz

* REFIN would be changed depending on input video format.
* Size is critical requirement. This is why they are choosing CDCE62002 instead of LMK series.

I know there is CDCE62002 GUI which can design loop filter and write register data to the EVM.
However, I could not set the loop bandwidth as low as 10Hz because the GUI shows an error "!" .
I would like to have your help how we should design CDCE62002 to pass SMPTE specification.

Best Regards,
Kawai

  • 0
    TI__Mastermind 32575 points
    Is the customer's input reference clock clean (e.g. crystal oscillator) or dirty (e.g. recovered clock from SERDES)?  If the ref clock to the PLL is dirty and needs a narrow PLL bandwidth down to 10 Hz to clean up jitter, it would require very large loop filter cap values (in milli-farad range, which is not practical to implement).  Therefore, I would not use this device for achieving PLL bandwidth below ~100 Hz.
     
    I suggest using LMK04xxx dual PLL jitter cleaner device with external 27 MHz VCXO to achieve 10 Hz or lower PLL bandwidth to effectively clean-up low-frequency timing jitter and meet the most stringent 3G-SDI SMPTE jitter specs.
     
    Regards,
    Alan
  • 0 in reply to Alan O
    Guru 19785 points

    Hi Alan-san,

    Thanks for giving me your advice.

    Input clock is not from the crystal oscillator, so I believe the it has the low frequency jitter.
    I understood that it would require mF order capacitor to narrow CDCE62002 loop bandwidth below 100Hz.

    To improve the jitter performance, I will ask customer to consider LMK04xxx.

    Thanks and Best Regards,
    Kawai