PLL not locking - CDCE62005 on DAC34SH84EVM

Basil Mohammed

Other Parts Discussed in Thread: CDCE62005

Hi,

I am using CDCE62005, on DAC34SH84EVM to provide the clock for DAC.

I am using a clock source (generates 96 Mhz, 1Vp-p) as the input to the EVM board. Thus, primary source is selected, PriRefDivider =2, RefDivider =3. I finally send 96 Mhz signal to DAC and FPGA.

But, on toggling the ENCAL for VCO, the PLL is not getting locked! ( Green LED not glowing ).
I am attaching the register settings below. Please look into it and help.

CDCE62005 Registers

Freq:0.000000MHz
Address Data
00 00400010
01 81060321
02 80120322
03 C1060303
04 C13C0304
05 00241A45
06 84BF4BF6
07 151877F7
08 20001808

Thanks a lot in advance,
Basil Mohammed

over 12 years ago

0 Alan O over 12 years ago

TI__Mastermind 32575 points

We will review this inquiry and provide some guidance soon. Thank you.

0 Basil Mohammed over 12 years ago in reply to Alan O

Prodigy 240 points

Thank you Alan. What I am trying to do over here is, provide a 96 MHz clock to ADC and DAC boards from the same source.At the ADC board, the clock will be directly fed to the ADC. In the DAC, I will have my input freq to CDCE62005 as 96M and output also as 96M.

Thanks,
Basil.

Clock & timing

Clock & timing forum

PLL not locking - CDCE62005 on DAC34SH84EVM