I am having trouble getting the DCLKout dividers to work as I expect on the LMK04828. I am using this chip with the ADS42JB69 A/D converter. Let's say I am working with DCLKout4. Starting from the ADS42JB69_LMK04828_settings.txt file that comes with the ADS42JB69EVM eval board, I find that both PLLs are locked. The VCO output is programmed to 3GHz. I'd like a 250 MHz clock, so I program DCLKout4_DIV to 12 by setting register 0x110 to 0x0c. What I see at the DCLKout4 output is a repeating pattern of pulses that are:
2ns on, 2ns off
2ns on, 2ns off
1ns on, 12ns off
Not what I expected. This is with DCLKout4_MUX set to "divide only." 0x113 = 0x0. OK, maybe I should try "divide with duty cycle correction and half step". 0x113 = 0x1. No difference
Next, I try a different divide value how about something well behaved like 16? 0x110 = 0x10
Now, I get pulses that look like
2ns on, 2ns off
3ns on, 14 ns off
What do I misunderstand about this divider?
