We have an issue with the CDCE62005. The problem is that we don't have a pll lock after a power on cycle and because of this the output frequencies were not stable. Our system consists of a C6678 DSP the CDCE62005 Clock generator which generates 50MHz and 20MHZ on its clock outs. We use a 25MHZ diferrential Crystal at the PRI_REF Input.Now we can get the correct output clock frequency,but after manual calibration,we can't get the rising edge of the pll lock signal.Here is the register value i configured.
E904 0320 //register0
E904 0301 //register1
E90E 0302 //register2
E90E 0303 //register3
E80E 0314 //register4
5000 8A75 //register5
84AE 0106 //register6
BD9A 3DF7 //register7
2000 5FF8 //register8
After I have configured register8,I wait for 500us,then I write Register6 the first time(only change R6.bit22 to 0),then write Register6 the second time(only change R6.bit22 to 1).During the whole time,the pll lock signal remain 0.What is the problom?