LMH1983 PLL4 frequency control

Hi John,

I have sent your query to the applications engineer supporting this product. Someone will get back to you shortly.

Regards

Arvind Sridhar

Hi John,

PLL4 VCO range is about 1.3G to 1.69GHz. The VCO4-Range determines the running frequency. Then we divide this down by 3,4 or 5, or 2 raised to power of the PLL4_DIV. 

However, i used your 29.5MHz and was not able to find the appropriate dividers in order to be within the VCO range. Could you please explain why you need 29.5MHz since it is not an integer multiple of 48KHz.

Hi Nasser,

my original circuit used an EL4585 PLL which generated a 29.5MHz clock which allowed me generate video graphics using a square pixel format (i.e. 1536 clocks(768*2) per 52us active period of a PAL line)

I would like the LMH1983 to generate the 29.5MHz clock so that I can continue to use other components of my original circuit.

regards

John

Hi John,

I think perhaps there is a way we can do this.

48X29.5MHz=1.42GHz This is within the range of the PLL4 VCO. Given this, it means you have to select your dividers as: 3X4X4. ISM125 = 4 & PLL4_DIV=2. Given this dividers you can change your PLL4 VCO range in order to get 29.5MHz on PLL4. Please let us know how it goes.

Regards,,nasser

Hi John,

I was able to generate 29.5MHz clock you were asking for. 

Please use the following register settings: 

Reg 0x39 = 0x21

Reg 0x34 = 0x22

Regards,,nasser

Hi Nasser,

These values worked fine in my application, thank you for the values.

Could you please explain how you arrived at these values, as I would also like to be able to a create 59.0MHz for an alternative operational mode for my circuit?

Is there also a utility program that you could provide that would generate these register values?

regards

John

Hi John,

Here is what i did. Please let me know your result and register contents as well:

The VCO range is divided down by the following equation:

3*IS125M*2^(PLL4_DIV)

The related registers are:

PLL4 VCO Range Register: 0x039

PLL4 VCO Divider Register: 0x34

Register 0x34[7:4]: This bits set PLL4_DIV variable

IS125M: Selects either divide by 4 or divide 5

Procedure for changing the PLL4 clock frequency:

1). Let’s say the desired frequency is 29.5MHz.

2). Divide the lower limit of the range(1.3G) by the desired frequency(i.e 29.5MHz). (1.3E9/29.5E6)= 44.1

3). Divide the upper limit of the range(1.6934GHz) by the desired frequency: (1.6934/29.5E6)=54.7

4). Given the above two results, it means 3*IS125M*2^(PLL4_DIV) must be a number between 45 and 54

5). Since IS125M either divide by 4 or divide by 5, the number between 45 to 54 has to be divisible either by 12 or 15

6). Further, given 2^(PLL4_DIV) is either 1,2,4,….., or 32768 AND divisor ratio has to be between 45 to 54, PLL4_DIV has to be 2

7). Thus 3*IS125M*2^(PLL4_DIV)= 3*4*2^(2)=3*4*4=48

8). Finally, we should set the VCO range frequency, Reg 0x39, to 1.416GHz to generate exactly 29.5MHz. Using a value of Reg 0x39 = 0x21 achieves this result

Regards,,nasser