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LMK04826 / number of Device and SYSREF clocks

Toshiyuki
Mastermind 7075 points
Other Parts Discussed in Thread: LMK04826

Hi,

Our customer is considering LMK04826 for JESD204B Compliant clock.

However, there is some possibility that their system is required 9 Differential Device Clocks and 9 SYSREF Clocks.

LMK04826 is configurable up to 7 Differential Device Clocks and 7 SYSREF Clocks.

Please let me know what the best solution is.

Best Regards,

Kato

  • 0
    TI__Mastermind 28550 points

    I'm afraid I don't have enough details to give a best solution, however it is worth noting that it is possible to use an LMK0482x as a JESD204B buffer by programming CLKin0 to be a SYSREF input and CLKin1 to be a device clock input.  This is a solution.

    To configure for JESD204 fanout buffer, for SYSREF:

    • CLKin0_OUT_MUX = 0 to feed CLKin0 to SYSREF path.
    • SYNC_MODE = 0 to disable SYSREF input from other source.
    • SYSREF_MUX = 0 to select CLKin0.
    • Plus other SYSREF output configuration.

    For device clock:

    • CLKin1_OUT_MUX = 0 to feed VCO_MUX
    • VCO_MUX = 3 to select from CLKin1 buffer (also used for external VCO mode)

    Figure 5-2. SYNC/SYSREF Clocking Paths from page 33 of datasheet illustrates the paths.

    Depending on reference source, it is also possible to put two LMK0482x in parallel, using 0-delay and SYSREF as a feedback to common SYSREF frequency source.

    73,

    Timothy

  • 0 in reply to Timothy T
    Mastermind 7075 points

    Timothy - san,

    Thank you for the explanation.

    Could you give me more details about how to put two LMK0482x in parallel?

    In addition, should we use 0-delay mode in this case?

    Best Regards,

    Kato

     

  • 0 in reply to Toshiyuki
    TI__Mastermind 28550 points

    Hello Kato-san,


    By configuring the device for 0-delay mode and feeding back the SYSREF frequency to PLL1, this allows the lowest frequency clocks between 2 or more LMK0482x to share phase.  When each LMK0482x SYNCs it's clocks - all clock outputs have deterministic phase alignment.  Provided the SYSREF frequency is the GCD or smaller of all the output frequencies of an LMK0482x, all phases will have alignment across parts.  You can use the info in Table 1-3 or 1-2 of datasheet to configure the actual 0-delay mode.


    When using parallel LMK0482x I suggest using dual loop for this because SYSREF is typically a low frequency which would otherwise limit PLL2 phase detector frequency.  To ensure best PLL performance high phase detector frequencies result in best PLL2 phase noise performance.  See slide 17 of Choosing Loop Bandwidth for PLLs http://e2e.ti.com/support/clocks/m/videos__files/664163.aspx to see this illustrated.  If your application can accept the worse PLL2 performance, then it is ok to use single PLL mode without VCXO.

    73,

    Timothy