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About the problem of the output of CDCE925.

Satoshi
Guru 19645 points
Other Parts Discussed in Thread: CDCE925

All the outputs of CDCE925 are set to 16MHz-only, and the measure is looked for.
 
Please look at attachment for details.

3302.Clock_problem.xlsx

I have the following ideas. Although a host writes a slave address (1100100) to CDCE925 first about the waveform of SDA and SCL, an acknowledge does not return from CDCE925.

Is it right although having given the command suddenly considers the cause?

(The 9th shot of SCLK thinks that CDCE returns an acknowledge by Low)  

Does below have a problem then?

-Start condition is NG.

-A device is different.

-The SDA drive by the side of a host.

-etc

Best regards,

Satoshi

  • 0
    TI__Expert 5325 points

    Hello Satoshi-san,

    you are correct the device does not return acknowledges at all. There can be several reasons for this:

    - in offset 0x02, SPICON: I2C interface disabled using EEPROM  (footnote 6 --> pull VDDOUT to LOW to override)

    - in offset 0x01, SLAVE_ADR: slave address bits accidentally reprogrammed; for debug: sweep A1:A0 bits on controller and check

    - in offset 0x06, BCOUNT: not enough bytes read in block transfer from device

    - VDD of 1.8V not fully ramped yet and I2C not fully functional

    I recommend to

    1) check general device operation. Are outputs switching?

    2) do an I2C read from the device as a crosscheck. Choose certain register to test read and write functionality (0x03 is output divider which you can crosscheck on the scope while operation)
    . CDCE925 has 0x00, MSB=1 . CDCE925L has MSB=0 as a crosscheck.


    Please let me know when you need more support. 5100.3302_Clock_problem_e2e_347852.xlsx

    Best regards,

    Patrick