Simulate Clock jitter of CDCE72010 using IBIS model

Ghorbel Mourad

Other Parts Discussed in Thread: CDCE72010

Hi,

I am using CDCE72010, and I am asking if I can simulate jitter using the IBIS model of the output and input clock buffers.

Thank you for your help.

Regards.

Mourad Ghorbel.

over 11 years ago

0 Arvind Sridhar over 11 years ago

TI__Mastermind 24205 points

Hi Mourad,

The IBIS model for the I/O can be used for perform board level signal integrity simulations and timing analysis. However for measuring jitter in time domain a high bandwidth, high memory depth, low sampling jitter oscillocope is recommended. For measuring jitter in frequency domain a phase noise analyzer is recommended.

Regards

Arvind Sridhar

Clock & timing

Clock & timing forum

Simulate Clock jitter of CDCE72010 using IBIS model