Hi,
I am planning to use the CDCE62002 Clock Generator, but due to the distances between the chips (10 cm), i am was going to use a clock distribution circuit - based on discrete logic.
My concern is that in implementing the relevant gates, that i may be introducing phae noise. I can see that i will introduce clock skew, but i am not sure about whether there will be phase noise introduced.
If phase noise is not introduced by a discrete logic, i then begin to consider whether the CDCE62002 with sub 1ps phase noise is really needs to be used.
I have searched the net, but unable to find any texts on the clock generators using a single crystal at the frequency needed, and an inverting logic gate with feedback.
Will such a circuit introduce phase noise - i can only surmise that the variation in the input thresholds will introduce such phase noise, but the duration of this variation etc., is not known - if this is the cause of phase noise ?.
Are there any texts on the optimal approach for a single frequency clock oscillator that has the same phase noise specification as the CDCE62002 ?.
Thanks.
Regards,
Richard.