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CDCM61002 Application Circuit diagram

Lee42634
Prodigy 10 points
Other Parts Discussed in Thread: CDCM61002

Hello All,

I am looking for an application circuit diagram for the CDCM61002, it is not in the datasheet.  I have checked out the EVM circuit schematic but it is very blurred.

Does anyone have?

Best regards

Lee

  • 0
    TI__Prodigy 515 points

    Lee,

    Apologies for the delay on the response for this.  Do you still need the above addressed or did you find the information you needed for the CDCM61002?

    Best regards,

    Brad

  • 0 in reply to Brad Ruzicka
    Prodigy 30 points

    Hi Brad,

    I've managed to sort out the cct for the CDCM61002.  But would like a circuit schematic as a reference check.

    Best Regards

    Lee

  • 0 in reply to Lee Isaac
    TI__Prodigy 515 points

    Lee,

    For a reference schematic for the CDCM61002, please take a look at the EVM User's Guide for the CDCM6100x below:

    http://www.ti.com/litv/pdf/scau027a

    We provide a snapshot of a reference circuit using the device on page 7 of this document.  In addition, the EVM User's Guide gives some additional recommendations on input and output termination, when needed.  Let me know if this is what you are looking for.

    Best regards,

    Brad

  • 0 in reply to Brad Ruzicka
    Intellectual 600 points

    Hi Brad,

           I have some question about the chip of CDCM61002:

          1.The input level of the chip is LVCMOS(3.3V), but Virtex-6 FPGA does not this standard. Can i directly drive the control signals of the CDCM61002,for example "OD0,OD1,OD2,RSTN..." through the FPGA(Bank vcco 2.5v).

          2.From the datasheet(page 25),i found that from the output of the chip to the LVDS determination,there is a 100ohm resistor ,why?when i directly connect to the FPGA,can i delete the resistor?

          3.Please give some advice about my design,the picture followed: