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CDCM7005-SP Sine Wave Support

Robin Gupta
Intellectual 760 points

Other Parts Discussed in Thread: CDCM7005-SP

Hi Team,

We are supporting one of our customer with CDCM7005-SP. They want to use CDCM7005-SP as clock buffer. The input of the Buffer will be fed at VCXO input and buffered to five outputs.

The input Fed to VCXO input is 75Mhz sine wave and is 2Vpk-pk.

I was looking in the datasheet for a minimum slew rate spec on VCXO input lines but couldn't fine so. Instead rise time spec was mentioned. Which as per the calculation for 75Mhz sine wave comes out to be 2.67ns for 20% to 80% which is within the datasheet spec of 3ns. Will this work for sine wave input?

Please let me know if this fine or any issues can arise because of sine wave input?

Thanks and Regards,

Robin Gupta.

  • 0
    TI__Mastermind 24205 points

    Hi Robin,

    The input amplitude specification for VINPP (Vcxo_in-Vcxo_inb) is 0.5V - 1.3V. Please ensure that your reference complies with this requirement.

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    TI__Intellectual 760 points

    Hi Arvind,

    Thanks for your quick reply.

    Input amplitude is sufficient I guess. My only concern is Sine wave input of 75Mhz. Do you think it won't be an issue for rise time/slew rate?

    Please confirm it once, as this is a critical opportunity we got with one of the Indian Space customer.

    It will be a great help if you can share any collected data with Sine Wave input with different frequencies, or if you can help us with any data?

    Thanks and Regards,

    Robin Gupta.

  • 0 in reply to Robin Gupta
    TI__Mastermind 24205 points

    Hi Robin,

    The specification of 1.3V max differential LVPECL input amplitude on the VCXO input should be met.

    As far as the slew rate is concerned, if the differential input amplitude is say 1V (pk-pk) and the sine wave input frequency is 75 MHz, the fastest slew rate achievable (around the crossing point) is 2*pi*75e6*1 = 0.475V/ns. This would imply a rise/fall time of roughly 1.26ns for 20%-80% of 1V (pk-pk) input which is well within the 3ns max specification.

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    TI__Intellectual 760 points

    Hi Arvind,

    Thanks for the clarfication.

    I have one small doubt regarding your slew rate calculation. For the 1Vpk-pk Sine wave input[Asin(wt)] the amplitude should be 0.5 right? The signal will be swinging from -0.5Volts to 0.5Volts right?

    If that's the case the slew rate will reduce by half and rise time will increase by twice? Please let me know if I am correct in my understanding?

    If this the case the rise time will get to 2.52ns which should be still ok for the device as it has a spec of 3ns rise time?

    Regards,

    Robin Gupta.

  • 0 in reply to Robin Gupta
    TI__Mastermind 24205 points

    Hi Robin,

    You are correct. I had a typo in my earlier email. It should have been 2V (pk-pk) or 1V peak amplitude. If 1V pk-pk then per the formula, rise time will be ~2.52ns which is still < 3ns.

    Regards

    Arvind Sridhar