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CDCE62005 Unable to read

Abhilasha Jain
Prodigy 30 points
Other Parts Discussed in Thread: CDCE62005

I'm trying to read the registers of CDCE62005 using SPI. The SPI is running on an FPGA. (coded in VHDL)

I send the following commands to read

0000000E

0000001E

0000002E

0000003E

0000004E

0000005E

0000006E

0000007E

0000008E

and this is the reply i get from the cdce

00000000

00000001

00000002

00000003

00000004

00000005

00000006

00000007

20009a08

Could anyone guide me on what's going wrong? Is it a timing issue or something else? Why only the 8th register (RAM) seems to giving any valid data?

  • 0
    TI__Mastermind 20900 points

    Hello Abhilasha,

    please make sure that SPI_LE is HIGH during power up. It ensures that the default register settings are loaded correctly.

    During SPI communication SPI_LE needs to be LOW.

    Note that you need to send LSB first.

    A REg2 read cycle captured on a oscilloscope:

    best regards,

    Julian

  • 0 in reply to Julian Hagedorn
    Prodigy 30 points

    Hi Julian,

    Thanks a lot for you reply!


    Inspired by your oscilloscope waveforms, I decided to capture my own.

    This is a reg8 read cycle. I'm only getting the address of the register I'm reading, rest of the bits are all zero.

    Can you give any information looking at the waveforms?

  • 0 in reply to Abhilasha Jain
    TI__Expert 5325 points

    Hello Abhilasha,

    looking at your scope shot you seem to be running <1MHz SPI_CLK. I assume setup and hold should not be an issue. Just to rule it out, can you provide more details about timing relation between SPI_LE, SPI_CLK and SPI_MOSI? (Maybe a zoom on the first bits with signals overlayed?)

    Can you provide more details about your power up sequence? As Julian suggested the SPI_LE needs to be high when releasing the !Power_Down pin (rising edge on !Power_Down pin and SPI_LE trigger loading from EEPROM).

    You can use the Register 8 as a perfect debug tool using the read only status information and crosscheck with the signals you apply to the device:

    - PLLLOCKPIN (R8.6)

    - !SLEEP (R8.7)

    - PRIACTIVITY, SECACTIVITY, AUXACTIVITY (R8.[27:25])

    Do you use an EVM from TI or is this already in your application / breadboard? Please try to tie the MODE_SEL (pin 33), SPI_LE (pin 25) and !Power_Down (pin 12) to 3.3V using pullup resistors. You can use the EVM as a reference. This way we can create clean levels when the FPGA comes up and the CDCE62005 is powered as well.

    Best regards,

    Patrick

  • 0 in reply to Patrick Kammermayer
    Prodigy 30 points

    Hello

    While looking into the timing of SPI_LE and SPI_CLK , I felt I should increased the duration of the latch (before miso sends the data) and everything seems to be working perfectly now!

    All registers read the expected data.

    Thankyou for your time!

    Regards

    Abhilasha