The soldering and Re flow parameters and Profile for Clock Repeaters and Synthesizers ICs of QFN Package

In addition to above query, I have added a JEDEC spec here. The FPGA, CPLD, DDR3 ICs used in my design all follow this spec and hence I could easily collect these parameters. Please let me know whether the QFN Package ICs of TI follow this spec?

3201.jstd020d-01 (1).pdf

Hi Vijetha,

I have forwarded your query to the right team within TI. We will get back to you soon.

Regard

Arvind Sridhar

Thank You Arvind Sridhar. It was useful document.

I also have another package TO-PMOD (Part LMZ12001TZ-ADJNOPB). Its clearly mentioned that the peak reflow temperature max is 245 deg C. May I know what is the minimum reflow temperature that can be maintained?

Also there are no details on Pre heat, Liquidus temperatures and ramp up rates for this package. I am not sure whether I can consider the values mentioned in the document you sent in previous reply for TO-PMOD Package. Can you provide these parameters (Pre heat temperature, Ramp up rates, Liquidus Temperature and Minimum Reflow Temperature).

Regards,

Vijetha

Hi Arvind,

Thank you for the details. I think now I got temperature profile for all packages I am using.  

But a basic question, whether the reflow profile for LLP package can be used for a QFN package? I got this doubt because the document provided (AN-1187, SNOA401R) was for LLP package and I feel LLP and QFN are different. So please clarify whether the temperature and Reflow parameters are same for LLP and QFN.

Regards,

Vijetha