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LMK04803 Questions

Takumi Suzuki1
Mastermind 8680 points

Hello,

I would like to ask 2 questions as below from my customer.

Q1) OSCout1 output condition when OSCout1 is disable

       As of now, OSCout1 output is "High" (3.3V) when this signal is disable.

       Is this condition correct?

Q2) PLL lock

       Now the customer is using this device with "Single-PLL" mode.

       In case of "0" delay setting of digital delay, PLL is not locked.

       I do not know the reason why PLL is not locked.

       Should I set/change something "loop-filter" setting to make PLL work well when delay is 0?

       Or something other reason?

I appreciate any advice for these questions.

Thank you.

Takumi

  • 0
    TI__Expert 5325 points

    Hello Suzuki-san,

    regarding

    Q1) Is the customer measuring this on the EVM?

    Q2) For the 0-delay mode you have to use the FEEDBACK_MUX to select an output clock signal and set EN_FEEDBACK_MUX. The output divider needs to be selected in a way it matches the frequency at the PFD. Try to keep N=1 to avoid ambiguities for the phase. You may power down the output stage (output signal type "power down"). The output path has to stay active (e.g. CLKOUT0_1_PD).

    Best regards,

    Patrick

  • 0 in reply to Patrick Kammermayer
    Mastermind 8680 points

    Patrick-san,

    Thank you very much for your reply.

    Q1) No, the customer observed "High"(3.3V) level on his board.

           The OSCout1 output pin is connected to buffer(LVDS) and pull-down to GND via 50ohm.

           In this condition, OSCout1 pin is High level when OSCout1 is disable.

           Could you tell me your idea about this?

     

    Q2) I see, I will tell  your advice to the customer.

    Best Regards,