I am using the CDCM1802 to convert a single ended clock, to a differential LVPECL clock. I have it configured as a divide by 1. I have multiple circuit boards where the part is not operating as expected. The output of the part is a divide by 2 of the input frequency. Input is 128 MHz, and the output is 64 MHz. I have reviewed the datasheet multiple times and have not determined what the issue is. I would appreciate some help with this. I am including Oscilloscope traces of the input and output waveforms, along with the schematic for the configuration of the part.
CDCM1802 Clock Application Problem
Conditions: Input Frequency = 128 MHz
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Input signal channel 1 (Yellow)
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Output signal channel 2 (Blue)
Schematic Circuit Connections
Issue:
I expected with the circuit configuration that the part would provide the same output frequency, as the input frequency, or in other words a divide by 1 operation. I have the EN pin floating, and the S0, and S1 pins connected to Ground.
