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At what time should I trigger lmk04828's SYSREF?

Moon Mars
Prodigy 70 points
Other Parts Discussed in Thread: ADS42JB69, LMK04828

Hi,

  I use ADS42JB69, lmk04828 and xilinx virtex6. I don't have a evaluation board. Here is a issue I sincerely hope you can help me. 

  The issue is: I plan to use lmk04828 to generate pulse(not continus) SYSREF signals for ADS42JB69 and FPGA. But I don't know at what time to trigger SYSREF pulses. 

   In Xilinx example design,  testbench generate SYSREF before SYNC~ deassert on purpose, but how can I ensure the SYSREF of LMK04828 is ahead of SYNC~ deassert? 

  I think the ADS42JB69 EVM has the same issue, so I sincerely hope you can help me.

  • 0
    TI__Mastermind 28550 points

    FPGA is RX device, so it is generating the SYNC~ signal, correct?  In I would suggest sending the SYSREF request, then waiting an two extra SYSREF periods than the number you request before releasing SYNC~.

    So if 10 MHz SYSREF and you request 4 pulses, SYSREF should be done by 6 * (1/10 MHz) from SYSREF request time.

    73,

    Timothy

  • 0 in reply to Timothy T
    TI__Mastermind 28550 points

    Another item is that the FPGA will also receive the SYSREF signal, so once it receives the SYSREF, then it would deassert the SYNC~.  This is how a DAC would work also.  DAC keeps SYNC~ high until SYSREF is received.  Then the DAC would lower SYNC~.

  • 0 in reply to Timothy T
    Prodigy 70 points

    Hi, Timothy:

      I'm very appreciated for your reply.

      Do you mean Xilinx jesd204b core will begin CGS(code group synchronize) only after receive the SYSFEF signal?If this is true, then I can deal with generating SYSREF signal like your suggest. 

      I have post the doubt on xilinx forum and no reply.  Maybe you have used the xilinx core with TI's product^_^

  • 0 in reply to Timothy T
    Prodigy 70 points

    Hi,Timothy:

     I have checked my last post and you are right.

     Thanks very much again.

    Best regards.