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CDCM7005 Feedback/Reference Phase Delay Doubts

Other Parts Discussed in Thread: CDCM7005

Hello,

I am working in a communication prototype using  the CDCM7005  which has programmable delays for reference and feedback clock inputs. The reference phase delay M is set with bits 24-26 of word 0 and the feedback phase delay N is set with bits 27-29 of word 0. I would like to use these delays to periodically align clock on Tx and Rx which are in different and independent boards, but both use CDCM7005 on their boards.

I would like to know what is the effective result on device outputs when I change the Phase Delay bits (24-29 of word 0). How much time does this delay take to effectively change the output.

The datasheet is not clear of what I must see after changing these delays and when I change them nothing seems to happen on output clock.

Should I configure the CDCM7005 in a specific way before changing the Phase Delay bits?

Thank you in advance,

Leonardo Ramalho

  • Hi Leonardo,

    The best way of viewing this change is to monitor the output clocks simultaneously as the reference clock or even VCXO. When triggering on the reference clock, the effective delay introduced in the loop (dependent on which values are set) will be seen as a delay on the output clocks.

    Note 1 on the Ref Delay M and Feedback Delay N Phase Adjustment Table (p23 of DS) states that Delay N will cause all Yx output to lead the reference by the set phase offset and Delay M will cause all Yx outputs to lag the reference by the set phase offset. Note that there is an inherent phase offset specified for each output type in the Device Characteristic table in the DS.

    Gabe

  • Dear Gabe,

    Thank you very much. Now we can see the delay on output.

    But we have another question:

    Is it possible to estimate in how much time the output is changed, after altering the Phase Delay? In seconds or clock cycles.

    Leonardo Ramalho

  • Hi Leonardo,

    This should be in the order of clock cycles.

    Gabe