LMX2581 Fastlock function

Jin,

The value of K is based on the fastlock current ratio.  For instance, if I was to use fastlock, you might set the charge pump to 8x gain (CPG=8) for normal operation and 31x gain for fastlock operation (FL_CPG=31x).  In this case, K=sqrt(31/8) ~ 2.   The resistor R2p is R2/ (sqrt(2) - 1).  So R2p = R2 in this case. 

In this case, the loop bandwidth would be twice during fastlock and the lock time wuld theoretically be half.  However, the actual improvement would less because of the VCO digital calibration and fastlock disengagement glitch.  So maybe a 20% reduciton in lock time.  For cases with a wide loop bandwidth and a lock time that is fast, say < 1 ms, you might not see any improvement.  For cases with a more narrow loop badwith and slower lock time, say >10 ms, they you would probably see more than 20% improement.

Regards,

Dean

Jin,

In regards to your question:

1.  FL_CPG should be set to 31.  However, for fastlock to work, you need to use a lower current when not in fastlock, like CPG=8.  If you use the lower CPG value, there might be some phase noise degradation relative to CPG=31 but this is the cost of using fastlock.

2.  FL_CPG must be greater than 31 for fastlock to be useful.

3.  For lock time, there are the elements of the VCO calbration time and the analog lock time.

The VCO calibration time can be anywhere from 10 us to 200 us, depending on setup.  The two things you can do to speed this up is increase the OSCin input frequency and also program the device to get the VCO caibration close.  I would focus on minimizing this as it costs no performance degadation and might be more effective.  To do this, you need to estimate what core and frequency to go next to.   For 1088 MHz, this is in the middle of VCO core 1, so set VCO_SEL=VCO1 and VCO_CAPCODE= 128.   When switching to 1252.5 MHz, this is in VCO Core 2, abut 2/3 of the way up, so set VCO_SEL=VCO 2 and set VCO_CAPCODE = 95.  I am getting this from table 5 on page 19 of the datasheet.   Set the VCO_SEL_MODE = "Start with VCO_SEL choice".

As for the analog lock time, since your lock time is pretty fast anyways, you might find that Fastlock is not nearly as helpful as the VCO calbiration trick above.  Also, it will cost you phase noise.   This is because the Fastlock creates a glitch when disengaged that has to settle out.  There is still a benefit to it in cases with longer lock times, but for this 200 us lock time, I think there might not be.   For the analog lock time, a wider loop bandwidth would probably be more beneficial and the higher charge pump current will improve the performance.  When designing for wider bandwidths, one of the restrictions is that the capacitors get too small, and this is where the charge pump current is better to be large.

So in conslusion, if I was the customer, I would use a higher input reference, use the method to speed up the VCO calibration, and design for a wider loop bandwidth with the highest charge pump current. 

Regards,
Dean

Jin,

Indeed, FL_CPG is set equal to 31, not greater than 31.  Although we allow FL_CPG to be progrmmed to anything, I have never seen a situation where it makes sense to use anything less than the maximum value.

The difference between enabling fastlock with FL_CPG=31 and just setting CPG=31 all the time is that the state of the FLout pin is grounded with the fastlock and not so with just setting CPG=31.  Other than this it is the same.

Regards,

Dean

The charge pump gain can be selected in the "PLL" block.  The lowest state is CLG=0 and the highest state is CPG=31.   For an optimized value, the highest gain is best for phase noise.  Clock Design tool defaults to the 24x state to allow some margin if one wants to adjust the charge pump gain to accomodate for changes in VCO gain.  If you want to use Fastlock, use the 8x state, whic corresponds to 0.88 mA, but I personally would just use the highest charge pump gain all the time and not use fastlock.  Instead, use the trick to speed up the VCO Calibration.

Regards,

Dean