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LMK04826 / SYSREF to Device Clock Alignment

Other Parts Discussed in Thread: LMK04826

Hi,

We have some questions about LMK04826 JESD204B operation.

Q1

tsJESD204B equals  ‐80ps(TYP) in the datasheet. What does the spec mean ?

I believe the rising edge of the SYSREF needs to be valid before the rising Device CLK edge.

Q2

Regarding Datasheet page37,

Please let me know the relationship between SYSREF and Device Clock.

Best Regards,

Kato

  • Hi Kato,

    The tsJESD204B = -80ps is the typical setup time from SYSREF to device clock under the conditions specified in the electrical table on page 20. This setup time however can be adjusted by through delays and mux settings, page 42 of datasheet has information on that.

    Regarding the section in page 37, in this step you basically set the phase difference between the device clock and the sysref clocks.

    step (a) lets you tune the device clock through digital delays. note these are in VCO cycles, so the delay time is according to your VCO frequency (page 32 of datasheet)

    step (b) is also digital delay but you adjust by half of the step sizes of step (a)

    step (c) is where you tune the SYSREF clock to the phase difference you want from the device clock

    step (d) configures the dividers so they are capable of being sync'd (by default they do not)

    step (e) perform the sync and your device clock and sysref clock will be locked to the phase relationship you have set.

    Please let me know if you have any other questions. Thanks!

    Regards,

    Brian Wang