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How to reduce frequency tolerance of OSC

Guru 15520 points
Other Parts Discussed in Thread: CDCE913

Hi,

I have a question about CDCE913.

Is it available to use CDCE913 for my following request:
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*Support TCXO clipped sine wave input
*TCXO frequency tolerance is 30ppm so that
 I want to reduce tolerance by Clock IC (0.2 to 0.05ppm)
*3 output
*output level : LVPECL or CMOS
*Max 27MHz output
/////////////////////////////////

If there are any other solution please suggest me the solution.

best regards,
g.f.

 

  • Hi,

    The device can support a TCXO clipped sine wave input as long the max rise time (20%-80%) of the reference signal is < 3ns. However, what you are trying to achieve is not possible. The accuracy of the output frequency from CDCE913 cannot be better than the accuracy of the reference clock.

    Regards

    Arvind Sridhar

  • Hi Arvind,

    Thank you for the reply.

    May I ask again to make me sure.
    Do you mean that the accuracy of the output frequency from not only CDCE913
    but all Clock IC can't be bettter than the accuracy of the reference clock?
    So, the accuracy of all clock IC's output will depend to the reference clock, am I right?

    best regards,
    g.f.

  • Hi g.f.

    Your understanding is correct. There are basically two errors: Reference clock error and PLL synthesis error. The reference clock error comes from the source which in this case is the TCXO. This cannot be removed by our device since it could potentially vary from part to part for the reference TCXO. The other type of error is the syntheis error due to the PLL fractional dividers. This is due to the part itself (CDCE913). For this particular device, the synthesis error can be made 0ppm by using the GUI to generate your frequencies. The GUI sets the internal dividers correctly to achieve 0 ppm error.

    Regards

    Arvind Sridhar

  • Hi Arvind,

    Thank you for the details.
    I understood.

    best regards,
    g.f.