CDCUN1208LP Phase Noise

Hi Tom,

I can look for this information for you. Is there a specific frequency or offsets you're interested in?

Gabe

Interested in 20MHz-6GHz frequency.

Do you mean you are interested in knowing the phase noise performance from 20 MHz to 6 GHz offsets?

Gabe

No, sorry. Not sure if you have a standard set of offset frequency ranges you plot against. Something like 10Hz to 4MHz offsets would be fine.

Hi Tom,

Here is typical data for the CDCUN1208LP with a clean 100 MHz reference. Input is from a clean 100 MHz differential oscillator and output 6 is measured via a balun.

Gabe

Thanks for the phase noise data. Would TI be willing to measure the phase noise of the 100MHz oscillator (or forward the oscillator/crystal datasheet) that they are using alone so that we can extrapolate the added phase noise of the buffer? We would also be very interested in the phase noise at a lower frequency like 19.2MHz/20MHz, 30MHz, or 38.4MHz/40MHz. Is it possible to plot the data as in the standard datasheet format?

Hi Tom,

This data shows only the additive jitter only (I had extrapolated the PN for you). I'll provide the PN reference for you below however.

I can collect this data if you need - which signaling type would you like this data for?

Below are the associated PN plots for this typical measurement.

Fig 1) Reference PN

Fig 2) HCSL PN

Fig 3) LVDS PN

Gabe

Thanks for the follow-up. Unfortunately this will severely limit our capabilities. We are looking for a buffer with 6-10dBc less than the source clock. The plots show this phase noise as greater than the source clock by a significant margin (~10dBc.) Does TI have better performing parts that I can look at?

I can give you recommendations based on your requirements (# of outputs, output format, etc)

Can you provide me with this info?

Gabe

Ideally I have a very specific configuration:

 Input: select between two possible inputs

Input Clock 1: 38.4MHz input clock 1.8V single ended

Input Clock 2: 38.4MHz input clock 3.3V single ended (I can resistor divide this down to 1.8V)

Outputs: desire the ability to enable/disable outputs individually

~4x 38.4MHz output clocks 1.8V single ended

~4x 38.4MHz output clocks 3.3V single ended

 Phase noise of around -160dBc above 10KHz, -140dBc or better at 1KHz and -120dBc or better at 100Hz.

 Please let me know if you need additional parameters specified. 

Hi Tom,

Do you need these signals as LVCMOS?

Gabe

Yes, LVCMOS.