Multiple LMK04828 Synchronization???

How are you using the LMK04828?  Dual loop or single loop?

73,

Timothy

I was thinking single loop? I was planning on using a low phase noise OCXO, ~400MHz, so the FPGAs could also use the 400MHz for their clock.

Hello Bob,

This is a rather involved topic I've not yet tested all the options for the single loop case.  Can you advise what your SYSREF frequency is going to be or might be?

There is a fairly simple way using dual loop 0-delay mode:

The simplest method to fan-out device clock and SYSREEF with multiple LMK0482x devices for JESD204B operation is to operate all LMK0482x devices in 0-delay dual loop mode with the SYSREF frequency as the feedback frequency to the PLL1 N divider.  Then as a reference to all the LMK0482x devices, fan-out a SYSREF based frequency to all LMK0482x devices.

Ways to generate this low frequency could include, but is not limited to using a XO or TCXO to provide this reference, or an FPGA – maybe it divides down a higher frequency or just creates a low frequency.  It is possible to use an LMK0482x to generate this SYSREF, but if so – I recommend using a device clock divider to generate the low frequency.  If the SYSREF divider was used, continuous operation of SYSREF can result in spurious on other device clock outputs, although in some application cases, this still could work.

The disadvantage of this technique is the requirement of a VCXO with each LMK0482x.  However, this may be perfectly acceptable - particularly if there is jitter on the reference clock which is distributed out to all the LMK0482x which needs to be cleaned anyway.

The advantage is that the phase of all SYSREFs of all LMK0482x is aligned using a closed loop 0-delay technique.  When SYSREF request is generated, all devices will sync up to the same LMFC clock, even if SYSREFs are generated at different times for the different devices.  If attempting to generate all SYSREFs at the exact same time, the timing all LMK0482x devices is with respect to the low frequency of the SYSREF.

--

As for single loop mode - 3 options:

(1) Do exactly the same thing as above, except that because you need to distribute the SYSREF frequency to OSCin and operate your PDF at the OSCin frequency, which would be low like 10 MHz, your performance may not be so great.

I'll send my other thoughts on this tomorrow...

73,

Timothy

Tim, I don't see how your recommendation above could work. I have a ~16 DAC boards that I need to beamform (precisely control the output signal timing/phase of each DAC relative to the others) to steer a RADAR beam. This means the waveforms must exit all the DACs (RADAR Antennas) simultaneously and be phase controlled relative to one another. Beamforming would also need to be done with my ~80 ADC boards on the RX side. All these boards may be seperated by up to 10 or 20 meters.

I planned on distributing a low-jitter reference clock of 400MHz to all the LMK04828 devices and create the 1200MHz DEVCLK and the SYSREF. Not sure what SYSREF freq I would need as that would be determined by the actual DAC and ADC parts, correct? Your input is greatly appreciated!

Hello Bob,

As I understand from your first post, you will have a master timing board, which generates reference and SYNC signal to ~100 boards.  Mostly ADCs but some DACs too.  Just wanted to clarify due to your next comment.

BobL said:

I planned on distributing a low-jitter reference clock of 400MHz to all the LMK04828 devices and create the 1200MHz DEVCLK and the SYSREF.

You will need to distribute a lower frequency than just 400 MHz to ensure all those SYSREF signals are deterministically aligned.  This could be your SYNC signal you mention.  Your first post suggests that some central timing board would generate both a reference clock (the 400 MHz) and SYNC signal to each board.

JESD204B provides deterministic timing within the LMFC period.  The SYSREF period is k * LMFC period where k = 1 to some integer.  By providing a reference frequency less than (/k) or equal to the LMFC, then phase alignment of all clock outputs is achieved by having a deterministic phase relationship between all output clocks...

In my suggestion above, one of the clocks (SYSREF divided output) will be the LMFC output frequency (or LMFC/k frequency) which ensures phase alignment at this 'low' frequency which aligns all converters.  The designer still needs to design the system so that it can work within the fact that the determinism doesn't extend to all time, but rather just the LMFC period.  Does that make sense?  At least that's my understanding of things for JESD204B.

BobL said:

Not sure what SYSREF freq I would need as that would be determined by the actual DAC and ADC parts, correct?

Correct.  SYSREF frequency relates to several things like number of frames, lanes, octets, etc.  Well technically the LMFC relates to number of frames, lanes, octets, etc and SYSREF frequency = LMFC / k.

If you were to distribute a 400 MHz reference to the LMK0482x devices on the ADC/DAC boards and a SYNC signal which connected to CLKin0, you could try and sync all the dividers together according to that SYNC signal, but you would be SYNCing against the high speed VCO clock which could result in some integer number of device clock cycles (+/-1?  +/-2?) variation between the different boards.  I'm guessing this is not precise enough for your system.  It may be possible to calibrate a single system using this technique, but the prior mentioned dual loop 0-delay system I think could give some better results.

Note that anytime you use an PLL, there is an analog phase comparison which exists.  This can change up to a few hundred ps in voltage, temperature, and process extremes.

--

A side note on controlling the phase between all the DACs and ADCs.  Consider using the LMK0482x for your reference generation.  Once locked up, you will have fixed phase between all ADCs/DACs.  You can use the digital delay (and possibly analog delay) to cause a phase shift in the reference vs. other references.  Then if you have another LMK04828 on the DAC or ADC card, you can implement a digital delay on the card, but with a slightly different frequency to get really fine digital delay (or delay) adjustments to help you tweak DAC sample time for exactly the same time.  So basically you could use 2400 MHz VCO on the ADC/DAC card and have a digital delay half step of 208.3 ps.  Then use a VCO of 2500 MHz on the master and have a digital delay half step of 200 ps.  Now by reducing half step on master card, then increasing half step on ADC/DAC card, a 8.3 ps step size is accomplished.  By using VCO frequencies closer or further apart, you can adjust this level of tuning resolution.  This should help you tune your DACs/ADCs together?

This vernier type technique can be used on a single device with device clock and analog delay, but the analog delay blocks have theoretically +/- 30% variation over PVT.

73,

Timothy

Tim, You are correct, I meant to type SYNC, not SYSREF. Not to confuse SYNC with *SYNC for Class 2 devices. I was thinking of just having a single edge for SYNC to Reset/Synchronize all the LMK0482x's at initialization.

What I'm also struggling with is how to distribute the Reference Clocks and SYNCs to all the LMK0482x's. These 10  meter long max. fanout connections will need to be very low jitter, picoseconds and length/phased matched. The Reference clock is sinewave, but the SYNC is logic. I've read that coax can be troublesome from a jitter standpoint due to temperature, pressure, vibration changes and etc.. Has anyone on your end used fiber for this type of distribution? I'm unsure if this would just shift my problems around. I've looked for fiber components that may work, but haven't had much luck. Semtec and Avago have some PCB-mount components.

Thanks for your time and patients! Bob