Other Parts Discussed in Thread: LMK04806
I have a LMK04806 that I'd like to use to generate 2500 MHz from a 20 MHz refclock with internal VCO.
OSCIN ist 20.000 MHz, very clean clock, no interruption.
PLL2 shall be set up to lock on it but it fails to do so. N=25, P=5 (making 125 together), R=1, N_CAL=25.
Loop filter is computed for PFD=20 MHz, 60 degrees, 120kHz BW (68pF || (3.3k+1.2nF)). PLL2_R verified to be 20.000 MHz. Polarity is negative (PLL2_CP_POL not set).
When writing register 30, the VCO will tune to 2510MHz and V_tune will be at 3.3V upper rail. Due to negative polarity, V_tune would have to be raised even higher to obtain lock which is not possible. V_tune shows clear signs of 20 MHz PD activity. Furthermore, it has negative dents of about 1usec with a rate of about 80kHz. This matches the difference frequency between 2510/125=20.080 MHz and the 20.000 MHz refclock.
It seems that the auto calibration does not do the proper thing..?
I can change to R=10, N=250, P=5, N_CAL=250 (same loop filter, not optimal of course), in order to lower the PD frequency by a factor of 10 to 2 MHz. Same result.
HOWEVER, if I set N=250, N_CAL=248, it sort of works (V_tune is at about 1.6V, VCO at 2500.0 MHz).
N_CAL=249 also works.
(Both not an option because I need to use PD freq of 20 MHz for better phase noise performance.)
Any ideas why the VCO calibration systematically finds a somewhat too large VCO frequency band? Or is there anything else "wrong"?
