40 MHz clock for a receiver

Hi Omid,

Did you have any specifications in mind for the 40 MHz reference? Integrated phase jitter?

Regards

Arvind

Hi Arvind,

Thanks a lot for the response.Here is a few specification.

- The clock amplitude(peak to peak): min:1V max:3V

- Phase noise: <140 dBc/Hz at 10khz offset, 145 at 100khz

- The clock should be able to drive 3 receiver chip. Each has input capacitor of  ~1.4 pF.

Thanks a lot

Omid

Hi Omid,

What is the preffered output type for the reference clock - Single ended or differential?

We have an 5X7 oscillator family in the design pipeline (Samples April 2015) that can support this frequency with different flavors of output drivers - LVPECL/LVDS and LVCMOS. Since you mention you need to drive 3 receiver loads with the output of this device, we recommend using a simple 1: 4 buffer like the CDCLVP1204 (LVPECL), CDCLVD1204 (LVDS) or CDCLVC1104 (LVCMOS)

Another option is to use CDCM6208 with a 25 MHz crystal reference.

Regards

Arvind

Dear Arvind,

Thanks a lot for your response and help.

The preferred output type is single ended.

Unfortunately, April is too late for my project. Is there any simple chip(such as a crystal driver) which use 40 Mhz crystal to generate 40 Mhz reference?

Regards,

Omid