CDCE18005 total jitter at 10MHz

Hello Federico,

we can achieve a low additive jitter. The total jitter depends on your application's noise floor and the input source.

Can you share which input source you have and where the device would be operating?

As you do not intend to use the dividers...

If you would not need pre-programming with the EEPROM, then maybe a pin-configurable device could be more attractive to your application?

For example LMK00306, CDCLVD1208 or CDCUN1208LP.

Best regards,

Patrick

Hello Patrick,

the good of CDCE18005 is the possibility to change interface type (and disable) each output pin and to select the input for each output: no other buffer (also from other suppliers) can do the same. Several components will be required to have the same capabilities.

I need 2 LVDS outputs and 4 LVCMOS outputs, 2 of them with off capability.

Two outputs will be the input to LMK04828 (for DAC) and to LMX2581 (for ADC) synthesizers; others to the up and down converters reference inputs and to the FPGA.

The inputs will be switched betwen a low noise TCXO (Connor Winfield series T) and the external reference input (coming from a rubidium clock) both at 10MHz. In order to lower jitter, the internal TCXO will be switched off when the external reference will be present (in order to eliminate crosstalk induced jitter)..

My fear is that the typical CDCE18005 jitter of 50fs is not retained at 10MHz, and/or the maximum jitter may be worst.

Best regards,

Federico

Hello Federico,

thanks for clarifying your application. Now I understand why the CDCE18005 is the best choice for you. We have some higher grade buffers which can switch output type or disable individually, but the source selection provides additional flexibility as you pointed out.

Let me check on some reference data which I can share with you.

Best regards,

Patrick

Hello Federico,

I made an example measurement in our lab at room temp for informational purposes:

Input Source (SMA100+HP8133A):

CDCE18005 output:

Best regards,

Patrick

(edit, fixed issue with picture upload)

Sorry Patrik,

but I dont see anything, neiter on the web page or the e-mail (images missing, opened with Thunderbird).

In any case, in the meantime I see other components datasheet, and it seems that lowering the frequency the jitter is higher: can you confirm this ? and if it is true, why ?

Best regards,

Federico

Hello Federico,

sorry for the issue with the image upload. I fixed it.

Best regards,

Patrick

Hello Patrick,

thanks for the measurement, but doing a simple calculation, the CDCE18005 RMS additive jitter results in this case 407,8 fs: is this value aligned (at the same 10MHz frequency) with other kind of fanout buffers, like LMK00101 for LVCMOS outputs or LMK00304/6 for LVECL/LVDS, or I can expect lower jitter using more of these components (cascaded or not) instead the CDCE18005 ?

Best regards,

Federico

Hello Federico,

let me check, same as for the CDCE18005, what data I have for the LMK-family of devices and come back to you.

Depending on the end application of your industry branch ... the CDCM7005-SP might be a possible option as well. It is extensively tested for robustness and you can use it as a buffer when you leave the feedback loop open...

Best regards,

Patrick