CDCM7005 Lock and Unlock

Hello Jin,

Is the customer using our EVM? or it's tested in their application directly?

Regards,

Ahmed

Ahmed
My customer tested application directly because the EVM BD of CDCM7005 is only available CDCM7005-SP which is not free of charge.
Thanks

Hi Jin,
Would you please clarify what is the intended frequency plan?
According to the values I see from the register values above (which is different than default) your divider settings are
M=2, N=3, P=8
the input reference frequency= 10MHz, the M value would dictate a PFD frequency of 5MHz.
Now the feedback divider is 24, with VCXO of 44.8MHz, your feedback frequency is 1.86667 MHz.

before looking into further details about schematic or configuration I need to understand the customer intended PFD frequency.

One valid PFD frequency is 400 kHz, this requires M=25, P=8, and N= 14, so NxP/N = 112/25 = 4.48 (=44.8/10)
if that suits the customer then settings should be set accordingly.

One other note is that the change charge pump preset bit should be used once in the beginning and released. lock can't be achieved with this bit set (Word 2, bit 3)

According to the schamtics I see a 3rd order filter, which (along with PLL settings I got from the control words) sets the loop bandwidth to 37Hz. is that the intended BW?

Hi Ahmed
Thanks to your answer, My customer cleared the problem Unlock.
Customer follwo your recommendation related to PFD.
Thanks