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How to select decap values for clock generator

Hi ,

How to determine what values and how many are to be used for a clock buffer. What all parameters should be considered, also is there any formula to calculate the required necessary value.

For ex. i have a 9 diff output with separate enable pins clock buffer.

TIA

  • Hi,
    Could you please let us know what device you are thinking of using in your design in order for us to provide you with the appropriate decoupling recommendation.
    RegardsArvind
  • Hi

    Am not using a TI part, but looking for a generic soluiton, am sorry if this forum is dedicated only for TI component discussion.
    Kindly let me know so that i can post in generic one if any.
  • Hi,

    If output frequencies are similar (as in the case of a simple buffer), and all VDDs pins on the device are connected internally, the recommended recoupling strategy is shown below

     

    This is just an example:

    The value of the C1 could be 0.1uF, C2 = 10uF and C3 = 0.1uF. The Ferrite Bead is selected based on its current rating, DC resistance and impedance at the frequency that needs to be filtered. C3 (local bypass) should be placed close to the device VDD pin. If you have 9 VDD pins on the device, connect 9, 0.1uF local bypass capacitors to ground right next to the VDDO pins.

    In general,

    A 10uF capacitor has a self resonant frequency of ~2 MHz and is effective upto ~15 inches from the target VDD

    A 1uF capacitor has a self resonant frequency of ~7 MHz and is effective upto ~4 inches from the target VDD

    A 0.1uF capacitor has a self resonant frequency of ~25 MHz and is effective upto ~1 inch from the target VDD

    A 0.01uF capacitor has a self resonant frequency of ~100 MHz and is effective upto ~0.3 inches from the target VDD


    Ensure that your 0.1uF local bypass capacitors are within an inch from the VDD pins of the device.

    Regards

    Arvind