LMK04828B clock design by code loader

Hello Soumya,

In general, after programming all the settings, please try to press Crtl + L. This command will load all settings from the GUI to the EVM.

in the CLKouts tab you can select between VCO0 and VCO1 (upper right corner, blue box). There you need to select VCO0 (2370 to 2630 MHz).

If you are using a standard EVM, then you will need to change the external VCXO from 122.88MHz to 100MHz.

Recommendation:

• PLL1_tab: set the PLL1_R=25 and PLL1_N=100 to have a PFD updated frequency of 1MHz. This will ease the Loop filter component design for low loop bandwidths. 
• PLL2_tab: set PLL2_R=1 and PLL2_N=12 and PLL2_N_Prescaler=2.

Best regards,

Julian

Hi Julian,

Thanks for your response.

I have already selected VCO0.

PLL1 & PLL2 section the VCO output is coming correct.

PLL1 is locking with a frequency of 100MHz.

PLL2 is locking with 2400MHZ.

In CLKout tab the reference OSCin frequency is 122.88MHz. It is not changing to 100MHz.

You have mentioned below statement in your answer.

"If you are using a standard EVM, then you will need to change the external VCXO from 122.88MHz to 100MHz"

Where to change ? I have changed in the PLL2 output & in the CLKout tab I tried to change the reference OSCin to 100MHz. But it is not changing.

Regards

Soumya

Hello Soumya,

The EVM has a 122.88MHz VCXO assembled. This needs to be exchanged to 100MHz VCXO. (external component)

Schematics can be found here: http://www.ti.com/lit/ug/snau145a/snau145a.pdf

 Best regards,

Julian

Hi Julian,

I tried to configure the PLL , Both the PLL is locking but the frequency is not coming.

I need register details for the PLL locking at a VCO frequency of 2400MHZ.

Clock input is CLKin0(LVCMOS) = 25MHz.
OSCin(LVPECL) =100MHz
VCO frequency is 2400MHz.

Is Any frequency calibration value needed for this PLL ?

Kindly share me the PLL register value.

Regards
Soumya

Hello Soumya,

Some questions first.

- Do you use the "off the shelve" EVM?

- Do you use a 100MHz VCXO?

In case you can answer the 2nd question with YES, then please see the mac file with the settings to generate 2.4GHz at DCLKout2 and 240MHz at DCLKout0.

/cfs-file/__key/communityserver-discussions-components-files/48/e2e_5F00_20150217.mac

Let me know if this helps.

Regards,

Julian

Hi Julian,

I have programmed the PLL by register value generated by my configuration.

The PLL2 was locking & PLL1 is not locking.

In the tool I observed, by changing R_COUNTER value in the PLL1 tab, CLKin1_R in the bit/pin mode is changing. As I have selected CLKin_SEL_MODE as CLKin0 Manual, the CLkin0_R  should change if I affect the R_COUNTER value.

So I suspected this is the cause for PLL1 is not locking.

Then I changed the manual mode to automatic mode & CLKin0 is coming by default. I found both the PLLs are locked & Now VCO frequency is locked by 2.4GHz.

My doubt is if I am changing the R_counter value in the PLL1 tab & I have selected CLKin_SEL_MODE as CLKin0 Manual, the CLKin0_R shall be changed. Why CLKin1_R is changing.

I will check with the .mac file given by you.

Regards

Soumya

Hello Soumya,

the PLL1_tab R counter is changing CLKin1_R, because this is the standard clock input on our EVM. If you are using CLKin0 then you need to manually change CLKin0_R to match the PLL1_tab.

Regards,

Julian