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LMK04816 fails to lock in dual (internal) PLL mode witzh 0-delay

Niels Koll
Expert 1940 points
Other Parts Discussed in Thread: LMK04816, CLOCKDESIGNTOOL, CODELOADER

Hello,

we try to use the LMK04816 in0-delay dual loop mode with internal PLL and internal feedback.

Input frequency at CLKin0 = 50MHz

External VCXO at 150MHz

Output frequency at all CLKoutXY shall be 50MHz.

Sounds easy, isn't it? But the LMK04816 refuses a lock. Here is my setting:

R0 => x"00000600"
R1 => x"00000601"
R2 => x"00000602"
R3 => x"00000603"
R4 => x"00000604"
R5 => x"00000605"
R6 => x"03160006"
R7 => x"03030007"
R8 => x"03030008"
R9 => x"55555549"
R10 => x"1140480A"
R11 => x"1400300B"
R12 => x"1BCC016C"
R13 => x"3B13106D"
R14 => x"1300000E"
R15 => x"0280400F"
R16 => x"01550410"
R24 => x"00000018"
R25 => x"01010019"
R26 => x"83A8001A"
R27 => x"1000009B"
R28 => x"0030009C"
R29 => x"0200031D"
R30 => x"0200031E"

We already verified the programming sequence by readback of the registers.

During our debugging we tried a VCXO of 50MHz and configured the chip for dual PLL mode (without 0-delay), resuting in a lock of both PLLs:

R 0 => x"00000600"
R 1 => x"00000661"
R 2 => x"00000662"
R 3 => x"00000663"
R 4 => x"00000664"
R 5 => x"00000665"
R 6 => x"03160006"
R 7 => x"03030007"
R 8 => x"03030008"
R 9 => x"55555549"
R10 => x"1140480A"
R11 => x"0400300B"
R12 => x"1B0C016C"
R13 => x"3B13106D"
R14 => x"1300000E"
R15 => x"0280400F"
R16 => x"01550410"
R24 => x"00000018"
R25 => x"01010019"
R26 => x"83A8001A"
R27 => x"1000009B"
R28 => x"0010009C"
R29 => x"0000037D"
R30 => x"0100037E"

I am aware that I should use EN_PLL2_REF_2X. But if I do, it causes that PLL2 does not lock.

Can you please have a look at the register maps and tell me what's wrong?

Regards,
Niels

  • 0
    TI__Mastermind 32575 points

    Make sure your PLL and Output divider settings are set accordingly for Dual PLL w/ 0-delay per section 9.2 of the datasheet:

    To obtain reasonable PLL1 loop filter capacitor values, I suggest to use PLL1 PFD frequency of 1 MHz and CPout1 current of 0.4 mA.  For PLL2, it is best to use the highest possible PFD frequency (up to 155 MHz max spec) and CPout2 current of 3.2 mA.  I suggest to use CLOCKDESIGNTOOL for PLL loop filter design and phase noise simulations.

    Improper PLL2_N_CAL setting (in Table 9-5) is commonly overlooked when programming 0-delay mode, but is important for proper VCO calibration.

    Also, please refer to Appendix H in the EVM user guide for PLL lock debugging hints:

    Regards,
    Alan

  • 0 in reply to Alan O
    Expert 1940 points

    Dear Alan,


    thank you for your reply.

    I used the CLOCKDESIGNTOOL for PLL loop filter designm and I am sure that my PLL and Output divider settings are set accordingly for Dual PLL w/ 0-delay per section 9.2 of the datasheet. But it's the first time I am using the LMK04816, and maybe my understanding of the data sheet is wrong.

    So I ask you, the TI clock experts, to please check my settings.

    I have a question regarding the picture you attached:

    In Table 9-2, you marked the line for enabled VCO Divider, but in Table 9-4 and Table 9-5 you marked the line for disabled VCO Divider. Is this just a typo, or are there some special reasons for that?

    Is the PLL2_N_CAL setting just equal to the PLL2_N setting, or is there something special about this register? I would be very glad if you could explain the background and usage of this register to me.
    In snlu107, page 36, I found the following statement:
    "The PLL2_N_CAL register contains the N value used for the VCO calibration routine. Except during 0-delay modes, the PLL2_N and PLL2_N_CAL registers will be exactly the same."
    For me this implies that PLL2_N and PLL2_N_CAL are NOT the same in 0-delay mode. But how do I have to set them in 0-delay mode?

    Is there anything that I have to consider about SYNC?

    Regards,
    Niels

  • 0 in reply to Niels Koll
    TI__Mastermind 32575 points
    CLOCKDESIGNTOOL assumes the device is operating in Dual PLL NON-0-delay mode, and does not take into account the output channel divider in the PLL1 feedback path (if you are using Nested Dual PLL 0-delay mode).

    In Nested Dual PLL 0-delay mode, PLL2_N and PLL2_N_CAL will be the same. PLL2_N_CAL is only different from PLL2_N in the case of Single PLL2 0-delay mode, because during VCO calibration the feedback path is through the PLL2_P and PLL2_N_CAL dividers and during normal 0-delay operation the feedback path is through the CLKoutX_Y_DIV and PLL_N dividers.

    If you're not using VCO divider, then VCO_DIV = 1 in the equations. Make sure the PLLx PFD (reference R path) is equal to PLLx PFD (feedback N path).

    For now, disable the SYNC feature so it doesn't complicate the debug process.

    If you used CODELOADER to generate your register settings, can you please send me the saved .MAC file? It is better analyze the settings in GUI format than manually decoding the register values.

    Regards,
    Alan
  • 0 in reply to Alan O
    Expert 1940 points

    Hi Alan,

    I hope you had a nice weekend.
    Please find attached the requested .mac file and a sketch what we want to do.

    By the way,
    during all our tests, we always see an PLL2 output clock 3% above the desired frequency, no lock, and CPout2 = 3.3V.
    If we manually modify the PLL2 divider to compensate this 3% missmatch, PLL2 locks but we don't get our desired output-frequency.

    Regards,
    Niels

    LMK04816_TAMC532_001.pdf

    LMK04816_TAMC532_001.txt 
    [SETUP]
ADDRESS=888
CLOCK=4
DATA=2
LE=6
PART=LMK04816B
PINPOSITION00=1
PINPOSITION01=7
PINPOSITION02=5
PINPOSITION03=10
[MODES]
NAME00=R0 (INIT)
VALUE00=2148925760
NAME01=R0
VALUE01=1536
NAME02=R1
VALUE02=1537
NAME03=R2
VALUE03=1538
NAME04=R3
VALUE04=1539
NAME05=R4
VALUE05=1540
NAME06=R5
VALUE06=1541
NAME07=R6
VALUE07=51773446
NAME08=R7
VALUE08=50528263
NAME09=R8
VALUE09=50528264
NAME10=R9
VALUE10=1431655753
NAME11=R10
VALUE11=289425418
NAME12=R11
VALUE12=335556619
NAME13=R12
VALUE13=466354540
NAME14=R13
VALUE14=991105133
NAME15=R14
VALUE15=318767118
NAME16=R15
VALUE16=41959439
NAME17=R16
VALUE17=22348816
NAME18=R24
VALUE18=24
NAME19=R25
VALUE19=16842777
NAME20=R26
VALUE20=2208825370
NAME21=R27
VALUE21=268435611
NAME22=R28
VALUE22=3145884
NAME23=R29
VALUE23=33555229
NAME24=R30
VALUE24=33555230
NAME25=R31
VALUE25=2031647
OSCIN00=150
EXTRA_PLL_N_DIV_1_00=1
OSCIN01=150
EXTRA_PLL_N_DIV_1_01=1
PINS=513
[BURST]
COUNT=0
[FLEXHASH]
HASHVALUE=0



  • 0 in reply to Niels Koll
    Expert 1940 points

    To the whole TI clock team and community:

    Since nobody is writing any replies to this topic, I will update it myself.

    Without your help, we achieved the correct output frequencies, but we do not see a PLl-lock.

    Since nobody answered to my last post (I wrote it a week ago), I will close this case and try a new one.

    Disappointed regards,
    Niels

  • 0 in reply to Niels Koll
    TI__Mastermind 32575 points
    My apologies for the delayed response. The codeloader setup and diagram you sent is helpful for me to understand the desired configuration.
    I will close this thread and respond to your new post to resolve the PLL lock status indicator issue.

    Regards,
    Alan