Hi,
I am using CDCE62005 in my design for generation of 5 LVDS clocks = 125 MHz using 50 MHz crystal oscillator in Secondary input.
Using the CDCE62005 GUI tool, we have created the register values and also with the suggestion of TI we have updated the files and getting the clocks successfully.
But few days back I am seeing following Issue:
The PLL Lock is not consistent in all the times. Some times the lock will be lost when we Power ON the system.
The Lock Detect Window value was set as 1.5 ns (as suggested by TI) (Reg [5.25 downto 5.22] = 0000)
Now we went back to the tool and checked the value and it was 3.4 ns (Reg [5.25 downto 5.22] = 0100). With this value we Powered ON-OFF multiple times and PLL Lock was lost somewhere near 8th time.
Later We changed it to Max value (28.6 ns - Reg [5.25 downto 5.22] = 1110) and did Power cycle for 15 times and did not see any inconsistency.
So from above observation I am summarising my queries below:
1. What is the meaning of Lock detection Window value, does it affect the PLL Lock? If Yes, How?
2. What is the criteria for selection of this value?
3. Can it be due to the above values of Lock Detection Window that PLL is losing lock?
4. Whether changing the Lock detection window value will cause any changes in the behaviour of the device?
5. What could be the possible reasons for PLL lock Inconsistency in general?
Please help me in finding the answer for the above queries.
Regards,
Vijetha
