To whom it may concern:
We are currently programming an LMK01020 using an FPGA directly over GPIO via the Serial Data Timing as outlined on page 8 of the LMK01000 family data sheet. Although we think we are sending the correct programming sequence, we would like verification from TI because we are not seeing outputs after successful programming. We are confident that the SPI module that we are using is valid because we see a noticeable current change when programming R14 POWERDOWN = 0. We write at 1 MHz. Our intended input clock is clock 1. I have copied our SPI settings in .mif format below. The SPI is written in line order below (00 to 09):
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WIDTH=32;
DEPTH=16;
ADDRESS_RADIX=HEX;
DATA_RADIX=BIN;
CONTENT BEGIN
00 : 10000000000000000000000000000000; --Program R0 with the reset bit (all other bits ignored)
01 : 00000000000000010000000000000000; --Program R0 to setup CLK0: enabled, bypassed, no divide, no delay
02 : 00000000000000110000000100000001; --Program R1 to setup CLK1: enabled, bypassed, divided by 2, no delay
03 : 00000000000000110000001000000010; --Program R2 to setup CLK2: enabled, bypassed, divided by 4, no delay
04 : 00000000000000010000000000000011; --Program R3 to setup CLK3: enabled, bypassed, no divide, no delay
05 : 00000000000000110001000000000100; --Program R4 to setup CLK4: enabled, bypassed, divided by 32, no delay
06 : 00000000000000110000010000000101; --Program R5 to setup CLK5: enabled, bypassed, divided by 8, no delay
07 : 00000000000000110000100000000110; --Program R6 to setup CLK6: enabled, bypassed, divided by 16, no delay
08 : 00000000000000110000101000000111; --Program R7 to setup CLK7: enabled, bypassed, divided by 20, no delay
09 : 01101000000000000000000000001110; --Program R14: CLKin_SELECT = clock 0, EN_CLKout_Global = 1, POWERDOWN = 0
0A : 00000000000000000000000000000000; --Intentionally left for expansion
0B : 00000000000000000000000000000000;
0C : 00000000000000000000000000000000;
0D : 00000000000000000000000000000000;
0F : 00000000000000000000000000000000;
END;
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I have included some screenshots of the hardware design, showing the input and some of the outputs. The output configuration is the same across all 8 outputs with the exception of one channel. On seven of the channels, the output is designed for LVPECL termination schemes, AC-coupled, then converted to LVDS configuration for interfacing to an FPGA. On one of the channels, both sides of the AC-coupling are terminated using the LVPECL termination scheme. The outputs are the same across the board. One issue to note is the use of 2.5 V on the SPI lines as those are what is available through the FPGA HSMC and the datasheet specifies that these voltages are appropriate since the VIH is 2.0 V for the SPI lines. Please correct me if that is incorrect.
