I'm currently working on getting the LMK04821 up and running on a new PCB. We're using registers 0x182 and 0x183 to read digital lock detect status from the two PLLs.
The datasheet, page 94 notes, for bit RB_PLL2_LD:
Read back 0: PLL2 DLD is high
Read back 1: PLL2 DLD is low.
The same goes for bit RB_PLL1_LD for the other PLL core.
This seems to indicate that the bit should be 0 when the PLL is locked. However, the behavior i'm observing is the other way around. It reads 0 for all configurations that should be impossible to lock for, and 1 only when I input a correct configuration.
Is this a polarity error in the datasheet?
I also tried outputting the DLD status on the Status_LDx pins, and they seem to support this theory. I always measure the same value on the status pin as i read from the readback pin, i.e. no polarity inversion.
