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CDCE72010/ phase difference of outputs after outputs were synchronised

Pavel Subrt
Prodigy 30 points


Hello. I use CDCE72010 on our boards. On some of them, there is 1.2ns additional delay on the random output after outputs were synchronised. Others boards are OK, all outputs are synchronised correctly. This additional delay is independent on the output divider settings or method of synchronization (external RESET pin or via SPI registers) and delay is the same on the boards with this behavior. Please has anybody the similar experience and found the solution. Thank you. Best regards, Pavel Subrt

  • 0
    TI__Expert 3520 points
    Hello Pavel,
    Please send one configuration where you experience this behavior (preferably as configuration file) . I understand you have multiple boards, do you experience this on the same board or randomly on all of them? The 1.2ns skew is normal if you have different output formats (LVCMOS and LVDS, or LVDS and LVPECL).
    Kind Regards,
    Ahmed
  • 0 in reply to Ahmed Noeman
    Prodigy 30 points
    Hello Ahmed, thank you for your reply. I have e.g. 10 boards (the same design, firmware and configuration). 8 boards are always correctly synchronised after calling „RESET“ - it's OK. Another board has always skew 1.2ns on U4 output after /RESET (the skew doesn't change and doesn't migrate to another output on the board) and the last board has always the skew 1.2ns on U7 output. All enabled outputs (U0, U1, U4, U7) on chip are LVPECL. This skew is always the same for the mentioned output and the board. I copied my register settings to EVM GUI and made configuration file for you. Thank you. Best Regards, Pavel

    [REGISTERS]
    REG0=802C0350
    REG1=81080221
    REG2=68040002
    REG3=68040003
    REG4=81080104
    REG5=68040005
    REG6=68040206
    REG7=81080117
    REG8=e90400d8
    REG9=01010c49
    REG10=01fc07fA
    REG11=0000058B
    REG12=61E09F0C
    [EVM_OUTPUTS]
    PWR_EN=1
    DEV_COMM_LED=1
    PLL_LOCK_LED=0
    CD_MODE_LED=1
    Y0_TERM=1
    Y1_TERM=1
    Y2_TERM=1
    Y3_TERM=1
    Y4_TERM=1
    Y5_TERM=1
    Y6_TERM=1
    Y7_TERM=1
    Y8_TERM=1
    Y9_TERM=1
    MODE_SEL=0
    REF_SEL=1
    AUX_SEL=1
    RESET=0
    POWER_DOWN=0
  • 0 in reply to Pavel Subrt
    TI__Expert 3520 points

    Hello Pavel,

    I'm trying to reproduce the issue, could you please send some information about input source, and input/output connections. a schematic snippet would be good.

    Regards,

    Ahmed