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CDCE62005 PLL UnLock

Ki Hyun Jeon
Prodigy 30 points
Other Parts Discussed in Thread: CDCE62005

Hi,

We designed a board with CDCE62005.

10MHz PRI LVDS input and 100MHz LVDS output.

I configure as shown in the attached file. but i just can't get a PLL Lock.

So, I changed the pll lock window, but the result is the same.

Plese tell me the check point.

Regards,

Kihyeon

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/CDCE62500.ini

  • 0
    TI__Expert 4400 points

    Your register map reflects a 25MHz LVPECL input, not a 10MHz LVDShttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/CDCE62005_5F00_2015_5F00_03_5F00_26.ini input. Here is the updated register map for a 10MHz LVDS input.

  • 0 in reply to Madhu Balasubramanian
    Prodigy 30 points

    Thank you Madhu for your reply.

    I was set to as you suggested.

    your suggested is Below.

    81840320
    EB020301
    EB020302
    EB020303
    210A0314
    10000A75
    860F0386
    FD0875F7
    20009E18

    But i changes to the setting suitable for my system. That is below.

    EB840320
    68020321
    68860302
    68860323
    68860314
    10000A75
    865F0386
    FD0875F7
    20009E18

    After Setting I try to Calibration VCO in manual mode Until Set to 1 REG 8.6.

    825F0386

    865F0386

    But doesn't change calibration word and still pll unlock.

    REG8 value is below.

    80009A08

    I use only primary input. However, synthesizer source indicates an auxiliary input.

    Can you tell me any problem in settings?