Hi,
I was set to as your suggested.
see it "https://e2e.ti.com/support/clocks/f/48/t/411629"
But still PLL unlock.
In my system, PRI clock is 10MHz.(LVDS)
I want to output 1 : 100MHz
So I was setting the registor value like below.
REGISTERS
0 EB060320
1 68840301
2 68860302
3 68860303
4 68860314
5 000C00F5
6 005E39E6
7 A9A0EB47
8 20009D98
That value generated on CDCE62005 EVM Software 1.4.8.
And then I checked the PLL Lock Pin and output clock. The PLL Lock Pin is unlock(low level).
How to solve this problem?
