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LMK04826 can’t be locked at -40℃

bin luo
Prodigy 40 points
Other Parts Discussed in Thread: LMK04826, CODELOADER

The reference to PLL1 from CLKin0(cpri recovery clock from FPGA) and CLKin1(test clock from signal generator).In normal operation, PLL1 uses CLKin0 for reference.PLL1 can’t be locked at -40℃,but unlock doesn’t happen every power reset time. When PLL1 is unlocked at -40℃, it can be locked by initializing LMK04826 registers. We only find one board has this problem. When PLL1 uses CLKin1 for reference, it is always locked at -40℃ after every power reset time.

How can we to confirm if this LMK04826 has problem?

 Thanks.

  • 0
    TI__Mastermind 24205 points

    Hi Bin,

    How do you confirm that PLL1 is unlocked? Are you monitoring the PLL1 Digital Lock Detect Output on the Status pin or checking the output frequency?

    Do you have a datasheet for the VCXO?

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    Prodigy 40 points

    We confirm if the PLL1 is locked by PLL1 Digital Lock Detect Output on the Status pin. The attachment is the datasheet for the VCXO.

    DATA-VG-4513CA-122.880000-GHC.pdf

  • 0 in reply to bin luo
    TI__Mastermind 24205 points

    Hi Bin,

    Can you try the following?

    Take a look at the picture below. Set the PLL1 DLD to Reserved in Codeloader tool as shown and connect the Status_LD1 pin to a scope to observe the resulting waveform. You should see a pulsed waveform. Measure the pulse width of the waveform and note this value.

    Fpfd is the phase detector frequency, Icp = Charge Pump Current, Vctrl = 3.3/2 = 1.65V and Tlock_window = 43ns (Register 0x15B - set to max datasheet value if not set already by default). Ri is the input impedance of the VCXO (min 100k from the datasheet of the VCXO)

    In general, the VCXO input impedance must satisfy the relationship shown in the pic below in order for the PLL1_DLD to indicate valid lock. If the relationship is violated, DLD will indicate unlock (even though technically the PLL might still be locked)

    Try increasing the charge pump to meet this relationship and the DLD should indicate lock.

     Hope this helps

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    Prodigy 40 points

    We test this problem by exchanging LMK04826 clock chips between A board(found this problem)  and B board(not found this problem).

    1.When A board + LMK04826 chip of B board tested at -40C, the PLL1 is always locked.

    2.When B board +  LMK04826 chip of A board tested at -40C, the PLL1 is sometimes unlocked.

    So this problem is caused by this bad LMK04826 chip. We will send this chip to TI to do failure analysis.